added rx bw in factory file, updated filesystem

LOorts-Aloxy · LOorts-Aloxy · commit a60b706d9f4f · 2019-05-21T09:33:06.000+02:00
diff --git a/stack/framework/inc/d7ap_fs.h b/stack/framework/inc/d7ap_fs.h
@@ -45,7 +45,7 @@
 #define D7A_FILE_FIRMWARE_VERSION_SIZE (2 + D7A_FILE_FIRMWARE_VERSION_APP_NAME_SIZE + D7A_FILE_FIRMWARE_VERSION_GIT_SHA1_SIZE)
 
 #define D7A_FILE_FACTORY_SETTINGS_FILE_ID 0x01
-#define D7A_FILE_FACTORY_SETTINGS_SIZE 1
+#define D7A_FILE_FACTORY_SETTINGS_SIZE 13
 
 #define D7A_FILE_ENGINEERING_MODE_FILE_ID 0x05
 #define D7A_FILE_ENGINEERING_MODE_SIZE  9
diff --git a/stack/modules/d7ap/d7ap_fs_data.c b/stack/modules/d7ap/d7ap_fs_data.c
@@ -182,61 +182,61 @@ __attribute__((used)) uint16_t files_offset[] = {
   output_system_file_offsets()
   ]]]*/
   0x4,	// UID - 0 (length 8))
-  0x18,	// FACTORY_SETTINGS - 1 (length 4))
-  0x28,	// FIRMWARE_VERSION - 2 (length 15))
-  0x43,	// DEVICE_CAPACITY - 3 (length 19))
-  0x62,	// DEVICE_STATUS - 4 (length 9))
-  0x77,	// ENGINEERING_MODE - 5 (length 9))
-  0x8c,	// VID - 6 (length 3))
-  0x9b,	// RFU_07 - 7 (length 0))
-  0xa7,	// PHY_CONFIG - 8 (length 9))
-  0xbc,	// PHY_STATUS - 9 (length 24))
-  0xe0,	// DLL_CONFIG - 10 (length 7))
-  0xf3,	// DLL_STATUS - 11 (length 12))
-  0x10b,	// NWL_ROUTING - 12 (length 1))
-  0x118,	// NWL_SECURITY - 13 (length 5))
-  0x129,	// NWL_SECURITY_KEY - 14 (length 16))
-  0x145,	// NWL_SSR - 15 (length 4))
-  0x155,	// NWL_STATUS - 16 (length 20))
-  0x175,	// TRL_STATUS - 17 (length 1))
-  0x182,	// SEL_CONFIG - 18 (length 6))
-  0x194,	// FOF_STATUS - 19 (length 10))
-  0x1aa,	// RFU_14 - 20 (length 0))
-  0x1b6,	// RFU_15 - 21 (length 0))
-  0x1c2,	// RFU_16 - 22 (length 0))
-  0x1ce,	// LOCATION_DATA - 23 (length 1))
-  0x1db,	// D7AALP_RFU_18 - 24 (length 0))
-  0x1e7,	// D7AALP_RFU_19 - 25 (length 0))
-  0x1f3,	// D7AALP_RFU_1A - 26 (length 0))
-  0x1ff,	// D7AALP_RFU_1B - 27 (length 0))
-  0x20b,	// D7AALP_RFU_1C - 28 (length 0))
-  0x217,	// D7AALP_RFU_1D - 29 (length 0))
-  0x223,	// D7AALP_RFU_1E - 30 (length 0))
-  0x22f,	// D7AALP_RFU_1F - 31 (length 0))
-  0x23b,	// ACCESS_PROFILE_0 - 32 (length 65))
-  0x288,	// ACCESS_PROFILE_1 - 33 (length 65))
-  0x2d5,	// ACCESS_PROFILE_2 - 34 (length 65))
-  0x322,	// ACCESS_PROFILE_3 - 35 (length 65))
-  0x36f,	// ACCESS_PROFILE_4 - 36 (length 65))
-  0x3bc,	// ACCESS_PROFILE_5 - 37 (length 65))
-  0x409,	// ACCESS_PROFILE_6 - 38 (length 65))
-  0x456,	// ACCESS_PROFILE_7 - 39 (length 65))
-  0x4a3,	// ACCESS_PROFILE_8 - 40 (length 65))
-  0x4f0,	// ACCESS_PROFILE_9 - 41 (length 65))
-  0x53d,	// ACCESS_PROFILE_10 - 42 (length 65))
-  0x58a,	// ACCESS_PROFILE_11 - 43 (length 65))
-  0x5d7,	// ACCESS_PROFILE_12 - 44 (length 65))
-  0x624,	// ACCESS_PROFILE_13 - 45 (length 65))
-  0x671,	// ACCESS_PROFILE_14 - 46 (length 65))
-  //[[[end]]] (checksum: 798913e0a6af67a14112df377fbc85a3)
+  0x18,	// FACTORY_SETTINGS - 1 (length 13))
+  0x31,	// FIRMWARE_VERSION - 2 (length 15))
+  0x4c,	// DEVICE_CAPACITY - 3 (length 19))
+  0x6b,	// DEVICE_STATUS - 4 (length 9))
+  0x80,	// ENGINEERING_MODE - 5 (length 9))
+  0x95,	// VID - 6 (length 3))
+  0xa4,	// RFU_07 - 7 (length 0))
+  0xb0,	// PHY_CONFIG - 8 (length 9))
+  0xc5,	// PHY_STATUS - 9 (length 24))
+  0xe9,	// DLL_CONFIG - 10 (length 7))
+  0xfc,	// DLL_STATUS - 11 (length 12))
+  0x114,	// NWL_ROUTING - 12 (length 1))
+  0x121,	// NWL_SECURITY - 13 (length 5))
+  0x132,	// NWL_SECURITY_KEY - 14 (length 16))
+  0x14e,	// NWL_SSR - 15 (length 4))
+  0x15e,	// NWL_STATUS - 16 (length 20))
+  0x17e,	// TRL_STATUS - 17 (length 1))
+  0x18b,	// SEL_CONFIG - 18 (length 6))
+  0x19d,	// FOF_STATUS - 19 (length 10))
+  0x1b3,	// RFU_14 - 20 (length 0))
+  0x1bf,	// RFU_15 - 21 (length 0))
+  0x1cb,	// RFU_16 - 22 (length 0))
+  0x1d7,	// LOCATION_DATA - 23 (length 1))
+  0x1e4,	// D7AALP_RFU_18 - 24 (length 0))
+  0x1f0,	// D7AALP_RFU_19 - 25 (length 0))
+  0x1fc,	// D7AALP_RFU_1A - 26 (length 0))
+  0x208,	// D7AALP_RFU_1B - 27 (length 0))
+  0x214,	// D7AALP_RFU_1C - 28 (length 0))
+  0x220,	// D7AALP_RFU_1D - 29 (length 0))
+  0x22c,	// D7AALP_RFU_1E - 30 (length 0))
+  0x238,	// D7AALP_RFU_1F - 31 (length 0))
+  0x244,	// ACCESS_PROFILE_0 - 32 (length 65))
+  0x291,	// ACCESS_PROFILE_1 - 33 (length 65))
+  0x2de,	// ACCESS_PROFILE_2 - 34 (length 65))
+  0x32b,	// ACCESS_PROFILE_3 - 35 (length 65))
+  0x378,	// ACCESS_PROFILE_4 - 36 (length 65))
+  0x3c5,	// ACCESS_PROFILE_5 - 37 (length 65))
+  0x412,	// ACCESS_PROFILE_6 - 38 (length 65))
+  0x45f,	// ACCESS_PROFILE_7 - 39 (length 65))
+  0x4ac,	// ACCESS_PROFILE_8 - 40 (length 65))
+  0x4f9,	// ACCESS_PROFILE_9 - 41 (length 65))
+  0x546,	// ACCESS_PROFILE_10 - 42 (length 65))
+  0x593,	// ACCESS_PROFILE_11 - 43 (length 65))
+  0x5e0,	// ACCESS_PROFILE_12 - 44 (length 65))
+  0x62d,	// ACCESS_PROFILE_13 - 45 (length 65))
+  0x67a,	// ACCESS_PROFILE_14 - 46 (length 65))
+  //[[[end]]] (checksum: 042b6478cc347b741c10b6de3153b1d9)
 };
 
 __attribute__((used)) uint8_t files_length[] = {
   /*[[[cog
   output_system_file_length()
   ]]]*/
   0x14,	// UID - 0)
-  0x10,	// FACTORY_SETTINGS - 1)
+  0x19,	// FACTORY_SETTINGS - 1)
   0x1b,	// FIRMWARE_VERSION - 2)
   0x1f,	// DEVICE_CAPACITY - 3)
   0x15,	// DEVICE_STATUS - 4)
@@ -282,7 +282,7 @@ __attribute__((used)) uint8_t files_length[] = {
   0x4d,	// ACCESS_PROFILE_12 - 44)
   0x4d,	// ACCESS_PROFILE_13 - 45)
   0x4d,	// ACCESS_PROFILE_14 - 46)
-  //[[[end]]] (checksum: e84fba5d8d3ec166279358e4bea2f101)
+  //[[[end]]] (checksum: bbc326f0152e2a522cb0548e2e8b11ad)
 };
 
 __attribute__((used)) uint8_t d7ap_permanent_files_data[FRAMEWORK_FS_PERMANENT_STORAGE_SIZE] LINKER_SECTION_FS_SYSTEM_FILE = {
@@ -297,8 +297,8 @@ __attribute__((used)) uint8_t d7ap_permanent_files_data[FRAMEWORK_FS_PERMANENT_S
   0x24, 0x23, 0xff, 0xff, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0, 0x0, 0x8, 
   0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 
   // FACTORY_SETTINGS - 1
-  0x24, 0x23, 0xff, 0xff, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x4, 
-  0x0, 0x14, 0x11, 0x1, 
+  0x24, 0x23, 0xff, 0xff, 0x0, 0x0, 0x0, 0xd, 0x0, 0x0, 0x0, 0xd, 
+  0x0, 0x0, 0x0, 0x28, 0xe4, 0x0, 0x1, 0x33, 0x36, 0x0, 0x1, 0xeb, 0xac, 
   // FIRMWARE_VERSION - 2
   0x24, 0x23, 0xff, 0xff, 0x0, 0x0, 0x0, 0xf, 0x0, 0x0, 0x0, 0xf, 
   0x0, 0x0, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 
@@ -434,7 +434,7 @@ __attribute__((used)) uint8_t d7ap_permanent_files_data[FRAMEWORK_FS_PERMANENT_S
   // ACCESS_PROFILE_14 - 46
   0x24, 0x23, 0xff, 0xff, 0x0, 0x0, 0x0, 0x41, 0x0, 0x0, 0x0, 0x41, 
   0x32, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xe, 0x56, 0xff, 0x0, 0x0, 0x0, 0x0, 0xe, 0x56, 0xff, 0x0, 0x0, 0x0, 0x0, 0xe, 0x56, 0xff, 0x0, 0x0, 0x0, 0x0, 0xe, 0x56, 0xff, 0x0, 0x0, 0x0, 0x0, 0xe, 0x56, 0xff, 0x0, 0x0, 0x0, 0x0, 0xe, 0x56, 0xff, 0x0, 0x0, 0x0, 0x0, 0xe, 0x56, 0xff, 0x0, 0x0, 0x0, 0x0, 0xe, 0x56, 0xff, 
-  //[[[end]]] (checksum: 149f22e1928490f8553b2faf3cdef27a)
+  //[[[end]]] (checksum: 3a946023cebf0bf007480483faf54484)
 };
 
 
diff --git a/stack/modules/d7ap/phy.c b/stack/modules/d7ap/phy.c
@@ -70,25 +70,28 @@
 #define BITRATE_L 9600 // bps
 #define FDEV_L    4800 // Hz
 // Carson's rule: 2 x fm + 2 x fd  = 9.600 + 2 x 4.800 = 19.2 kHz
-// assuming 10 ppm crystals gives max error of: 2 * 10 ppm * 868 = 17.36 kHz
-// => BW > 19.2 + 17.36 kHz => > 36.5 kHZ.
-#define RXBW_L    36500 //Hz
+// assuming 1 ppm crystals gives max error of: 2 * 1 ppm * 868 = 1.736 kHz
+// => BW > 19.2 + 1.736 kHz => > 20.936 kHZ. 
+// This results in 10.468 kHz on a single sideband.
+// #define RXBW_L    10468 //Hz
 
 // normal rate
 #define BITRATE_N 55555 // bps
 #define FDEV_N    50000 // Hz
 // Carson's rule: 2 x fm + 2 x fd  = 55.555 + 2 x 50 = 155.555 kHz
-// assuming 10 ppm crystals gives max error of: 2 * 10 ppm * 868 = 17.36 kHz
-// => BW > 155.555 + 17.36 => 172.91 KHz
-#define RXBW_N   172910 //Hz
+// assuming 1 ppm crystals gives max error of: 2 * 1 ppm * 868 = 1.736 kHz
+// => BW > 155.555 + 1.736 => 157.291 kHz. 
+// This results in 78.646 kHz on a single sideband.
+// #define RXBW_N   78646 //Hz
 
 // high rate
 #define BITRATE_H 166667 // bps
 #define FDEV_H     41667 // Hz
 // Carson's rule: 2 x fm + 2 x fd  = 166.667 + 2 x 41.667 = 250 kHz
-// assuming 10 ppm crystals gives max error of: 2 * 10 ppm * 868 = 17.36 kHz
-// => BW > 250 + 17.36 kHz => > 267.36 kHZ.
-#define RXBW_H    267360 //Hz
+// assuming 1 ppm crystals gives max error of: 2 * 1 ppm * 868 = 1.736 kHz
+// => BW > 250 + 1.736 kHz => 251.736 kHz.
+// This results in 125.868 kHz on a single sideband.
+// #define RXBW_H    125868 //Hz
 
 #define LORA_T_SYMBOL_SF9_MS 4.096 // based on SF9 and 125k BW
 #define LORA_T_PREAMBE_SF9_MS (8 + 4.25) * LORA_T_SYMBOL_SF9_MS // assuming 8 symbols for now
@@ -125,6 +128,11 @@ static channel_id_t default_channel_id = {
 
 static channel_id_t current_channel_id = EMPTY_CHANNEL_ID;
 
+static uint32_t rx_bw_lo_rate;
+static uint32_t rx_bw_normal_rate;
+static uint32_t rx_bw_hi_rate;
+static bool rx_bw_changed = false;
+
 static uint8_t gain_offset = 0;
 
 /*
@@ -370,10 +378,12 @@ static void configure_eirp(eirp_t eirp)
 }
 
 static void configure_channel(const channel_id_t* channel) {
-    if(phy_radio_channel_ids_equal(&current_channel_id, channel)) {
+    if(phy_radio_channel_ids_equal(&current_channel_id, channel) && !rx_bw_changed) {
         return;
     }
 
+    rx_bw_changed = false;
+
     // configure modulation settings
     if(channel->channel_header.ch_class == PHY_CLASS_LO_RATE)
     {
@@ -382,7 +392,7 @@ static void configure_channel(const channel_id_t* channel) {
             hw_radio_set_tx_fdev(FDEV_L);
         else
             hw_radio_set_tx_fdev(0);
-        hw_radio_set_rx_bw_hz(RXBW_L);
+        hw_radio_set_rx_bw_hz(rx_bw_lo_rate);
         hw_radio_set_preamble_size(PREAMBLE_LOW_RATE_CLASS * 8);
     }
     else if(channel->channel_header.ch_class == PHY_CLASS_NORMAL_RATE)
@@ -392,7 +402,7 @@ static void configure_channel(const channel_id_t* channel) {
             hw_radio_set_tx_fdev(FDEV_N);
         else
             hw_radio_set_tx_fdev(0);
-        hw_radio_set_rx_bw_hz(RXBW_N);
+        hw_radio_set_rx_bw_hz(rx_bw_normal_rate);
         hw_radio_set_preamble_size(PREAMBLE_NORMAL_RATE_CLASS * 8);
     }
     else if(channel->channel_header.ch_class == PHY_CLASS_HI_RATE)
@@ -402,7 +412,7 @@ static void configure_channel(const channel_id_t* channel) {
             hw_radio_set_tx_fdev(FDEV_H);
         else
             hw_radio_set_tx_fdev(0);
-        hw_radio_set_rx_bw_hz(RXBW_H);
+        hw_radio_set_rx_bw_hz(rx_bw_hi_rate);
         hw_radio_set_preamble_size(PREAMBLE_HI_RATE_CLASS * 8);
     }
 
@@ -449,8 +459,14 @@ void fact_settings_file_change_callback()
     d7ap_fs_read_file(D7A_FILE_FACTORY_SETTINGS_FILE_ID, 0, fact_settings, D7A_FILE_FACTORY_SETTINGS_SIZE);
 
     gain_offset = (int8_t)fact_settings[0];
+    rx_bw_lo_rate = __builtin_bswap32(*((uint32_t*)(fact_settings+1)));
+    rx_bw_normal_rate = __builtin_bswap32(*((uint32_t*)(fact_settings+5)));
+    rx_bw_hi_rate = __builtin_bswap32(*((uint32_t*)(fact_settings+9)));
+
+    DPRINT("rx bw low rate is %i, normal rate is %i, high rate is %i\n", rx_bw_lo_rate, rx_bw_normal_rate, rx_bw_hi_rate);
+    DPRINT("gain offset set to %i\n", gain_offset);
 
-    DPRINT("gain set to %i\n", gain_offset);
+    rx_bw_changed = true;
 }
 
 
