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Merge branch '79-rx-bw-in-files-2' into 'master'
Resolve "RX BW in files" Closes Sub-IoT#79 See merge request aloxy/oss-7!49
2 parents 547020d + 9912890 commit c634fd1

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7 files changed

+106
-119
lines changed

7 files changed

+106
-119
lines changed

‎stack/framework/hal/chips/netdev_driver/netdev.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -355,9 +355,9 @@ void hw_radio_enable_preloading(bool enable)
355355
netdev->driver->set(netdev, NETOPT_PRELOADING, &netopt_enable, sizeof(netopt_enable_t));
356356
}
357357

358-
void hw_radio_set_tx_power(uint8_t eirp)
358+
void hw_radio_set_tx_power(int8_t eirp)
359359
{
360-
netdev->driver->set(netdev, NETOPT_TX_POWER, &eirp, sizeof(uint8_t));
360+
netdev->driver->set(netdev, NETOPT_TX_POWER, &eirp, sizeof(int8_t));
361361
}
362362

363363
void hw_radio_set_rx_timeout(uint32_t timeout)

‎stack/framework/hal/chips/sx127x/sx127x.c

Lines changed: 1 addition & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -53,53 +53,6 @@
5353
#define FG_THRESHOLD 32
5454
#define FIFO_AVAILABLE_SPACE FIFO_SIZE - FG_THRESHOLD
5555

56-
// modulation settings
57-
// lo rate
58-
// BR 0x0D05 => 9600.960 bps
59-
#define BITRATEMSB_L 0x0D
60-
#define BITRATELSB_L 0x05
61-
// Fdev => 4.8 kHz
62-
#define FDEVMSB_L 0x00
63-
#define FDEVLSB_L 0x4F
64-
// Carson's rule: 2 x fm + 2 x fd = 9.600 + 2 x 4.800 = 19.2 kHz
65-
// assuming 1 ppm crystals gives max error of: 2 * 1 ppm * 868 = 1.736 kHz
66-
// => BW > 19.2 + 1.736 kHz => > 20.936 kHZ.
67-
// This results in 10.468 kHz on a single sideband.
68-
// Closest possible value is 10.4 kHz. This is an actual ppm of 0.92. ((2 << 3) | 5)
69-
// Other possibility is 12.5 kHz. This is an actual ppm of 3.34. ((1 << 3) | 5)
70-
#define RXBW_L ((2 << 3) | 5) // TODO validate sensitivity / xtal accuracy tradeoff
71-
72-
// normal rate
73-
// BR 0x0240 => 55555.55555 bps
74-
#define BITRATEMSB_N 0x02
75-
#define BITRATELSB_N 0x40
76-
// Fdev => 49.988 kHz
77-
#define FDEVMSB_N 0x03
78-
#define FDEVLSB_N 0x33
79-
// data rate 55.542 kBaud
80-
// Carson's rule: 2 x fm + 2 x fd = 55.555 + 2 x 50 = 155.555 kHz
81-
// assuming 1 ppm crystals gives max error of: 2 * 1 ppm * 868 = 1.736 kHz
82-
// => BW > 155.555 + 1.736 => 157.291 kHz.
83-
// This results in 78.646 kHz on a single sideband.
84-
// Closest possible value is 83.3 kHz. This is an actual ppm of 6.36.
85-
// TODO bit too high, next step is 200, validate sensitivity / xtal accuracy tradeoff
86-
#define RXBW_N ((2 << 3) | 2)
87-
88-
// hi rate
89-
// BR 0x00C0 => 166666.667 bps
90-
#define BITRATEMSB_H 0x00
91-
#define BITRATELSB_H 0xC0
92-
// Fdev => 41.667 kHz
93-
#define FDEVMSB_H 0x02
94-
#define FDEVLSB_H 0xAA
95-
// Carson's rule: 2 x fm + 2 x fd = 166.667 + 2 x 41.667 = 250 kHz
96-
// assuming 1 ppm crystals gives max error of: 2 * 1 ppm * 868 = 1.736 kHz
97-
// => BW > 250 + 1.736 kHz => 251.736 kHz.
98-
// This results in 125.868 kHz on a single sideband.
99-
// Closest possible value is 125 kHz. This is an actual ppm of 0. ((0 << 3) | 2)
100-
// Other possibility is 166.7 kHz. This is an actual ppm of 48.04. ((2 << 3) | 1)
101-
#define RXBW_H ((0 << 3) | 2) // TODO validate sensitivity / xtal accuracy tradeoff
102-
10356
#if defined(FRAMEWORK_LOG_ENABLED) && defined(FRAMEWORK_PHY_LOG_ENABLED)
10457
#define DPRINT(...) log_print_stack_string(LOG_STACK_PHY, __VA_ARGS__)
10558
#define DPRINT_DATA(...) log_print_data(__VA_ARGS__)
@@ -932,7 +885,7 @@ void hw_radio_enable_preloading(bool enable) {
932885
enable_preloading = enable;
933886
}
934887

935-
void hw_radio_set_tx_power(uint8_t eirp) { // TODO signed
888+
void hw_radio_set_tx_power(int8_t eirp) { // TODO signed
936889
if(eirp < -5) {
937890
eirp = -5;
938891
DPRINT("The given eirp is too low, adjusted to %d dBm, offset excluded", eirp);

‎stack/framework/hal/inc/hwradio.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -447,7 +447,7 @@ bool hw_radio_is_rx(void);
447447
void hw_radio_enable_refill(bool enable);
448448
void hw_radio_enable_preloading(bool enable);
449449

450-
void hw_radio_set_tx_power(uint8_t eirp); // TODO signed
450+
void hw_radio_set_tx_power(int8_t eirp); // TODO signed
451451

452452
void hw_radio_set_rx_timeout(uint32_t timeout);
453453

‎stack/framework/inc/d7ap_fs.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,7 @@
4545
#define D7A_FILE_FIRMWARE_VERSION_SIZE (2 + D7A_FILE_FIRMWARE_VERSION_APP_NAME_SIZE + D7A_FILE_FIRMWARE_VERSION_GIT_SHA1_SIZE)
4646

4747
#define D7A_FILE_FACTORY_SETTINGS_FILE_ID 0x01
48-
#define D7A_FILE_FACTORY_SETTINGS_SIZE 1
48+
#define D7A_FILE_FACTORY_SETTINGS_SIZE 13
4949

5050
#define D7A_FILE_ENGINEERING_MODE_FILE_ID 0x05
5151
#define D7A_FILE_ENGINEERING_MODE_SIZE 9

‎stack/modules/d7ap/d7ap_fs_data.c

Lines changed: 52 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -182,61 +182,61 @@ __attribute__((used)) uint16_t files_offset[] = {
182182
output_system_file_offsets()
183183
]]]*/
184184
0x4, // UID - 0 (length 8))
185-
0x18, // FACTORY_SETTINGS - 1 (length 4))
186-
0x28, // FIRMWARE_VERSION - 2 (length 15))
187-
0x43, // DEVICE_CAPACITY - 3 (length 19))
188-
0x62, // DEVICE_STATUS - 4 (length 9))
189-
0x77, // ENGINEERING_MODE - 5 (length 9))
190-
0x8c, // VID - 6 (length 3))
191-
0x9b, // RFU_07 - 7 (length 0))
192-
0xa7, // PHY_CONFIG - 8 (length 9))
193-
0xbc, // PHY_STATUS - 9 (length 24))
194-
0xe0, // DLL_CONFIG - 10 (length 7))
195-
0xf3, // DLL_STATUS - 11 (length 12))
196-
0x10b, // NWL_ROUTING - 12 (length 1))
197-
0x118, // NWL_SECURITY - 13 (length 5))
198-
0x129, // NWL_SECURITY_KEY - 14 (length 16))
199-
0x145, // NWL_SSR - 15 (length 4))
200-
0x155, // NWL_STATUS - 16 (length 20))
201-
0x175, // TRL_STATUS - 17 (length 1))
202-
0x182, // SEL_CONFIG - 18 (length 6))
203-
0x194, // FOF_STATUS - 19 (length 10))
204-
0x1aa, // RFU_14 - 20 (length 0))
205-
0x1b6, // RFU_15 - 21 (length 0))
206-
0x1c2, // RFU_16 - 22 (length 0))
207-
0x1ce, // LOCATION_DATA - 23 (length 1))
208-
0x1db, // D7AALP_RFU_18 - 24 (length 0))
209-
0x1e7, // D7AALP_RFU_19 - 25 (length 0))
210-
0x1f3, // D7AALP_RFU_1A - 26 (length 0))
211-
0x1ff, // D7AALP_RFU_1B - 27 (length 0))
212-
0x20b, // D7AALP_RFU_1C - 28 (length 0))
213-
0x217, // D7AALP_RFU_1D - 29 (length 0))
214-
0x223, // D7AALP_RFU_1E - 30 (length 0))
215-
0x22f, // D7AALP_RFU_1F - 31 (length 0))
216-
0x23b, // ACCESS_PROFILE_0 - 32 (length 65))
217-
0x288, // ACCESS_PROFILE_1 - 33 (length 65))
218-
0x2d5, // ACCESS_PROFILE_2 - 34 (length 65))
219-
0x322, // ACCESS_PROFILE_3 - 35 (length 65))
220-
0x36f, // ACCESS_PROFILE_4 - 36 (length 65))
221-
0x3bc, // ACCESS_PROFILE_5 - 37 (length 65))
222-
0x409, // ACCESS_PROFILE_6 - 38 (length 65))
223-
0x456, // ACCESS_PROFILE_7 - 39 (length 65))
224-
0x4a3, // ACCESS_PROFILE_8 - 40 (length 65))
225-
0x4f0, // ACCESS_PROFILE_9 - 41 (length 65))
226-
0x53d, // ACCESS_PROFILE_10 - 42 (length 65))
227-
0x58a, // ACCESS_PROFILE_11 - 43 (length 65))
228-
0x5d7, // ACCESS_PROFILE_12 - 44 (length 65))
229-
0x624, // ACCESS_PROFILE_13 - 45 (length 65))
230-
0x671, // ACCESS_PROFILE_14 - 46 (length 65))
231-
//[[[end]]] (checksum: 798913e0a6af67a14112df377fbc85a3)
185+
0x18, // FACTORY_SETTINGS - 1 (length 13))
186+
0x31, // FIRMWARE_VERSION - 2 (length 15))
187+
0x4c, // DEVICE_CAPACITY - 3 (length 19))
188+
0x6b, // DEVICE_STATUS - 4 (length 9))
189+
0x80, // ENGINEERING_MODE - 5 (length 9))
190+
0x95, // VID - 6 (length 3))
191+
0xa4, // RFU_07 - 7 (length 0))
192+
0xb0, // PHY_CONFIG - 8 (length 9))
193+
0xc5, // PHY_STATUS - 9 (length 24))
194+
0xe9, // DLL_CONFIG - 10 (length 7))
195+
0xfc, // DLL_STATUS - 11 (length 12))
196+
0x114, // NWL_ROUTING - 12 (length 1))
197+
0x121, // NWL_SECURITY - 13 (length 5))
198+
0x132, // NWL_SECURITY_KEY - 14 (length 16))
199+
0x14e, // NWL_SSR - 15 (length 4))
200+
0x15e, // NWL_STATUS - 16 (length 20))
201+
0x17e, // TRL_STATUS - 17 (length 1))
202+
0x18b, // SEL_CONFIG - 18 (length 6))
203+
0x19d, // FOF_STATUS - 19 (length 10))
204+
0x1b3, // RFU_14 - 20 (length 0))
205+
0x1bf, // RFU_15 - 21 (length 0))
206+
0x1cb, // RFU_16 - 22 (length 0))
207+
0x1d7, // LOCATION_DATA - 23 (length 1))
208+
0x1e4, // D7AALP_RFU_18 - 24 (length 0))
209+
0x1f0, // D7AALP_RFU_19 - 25 (length 0))
210+
0x1fc, // D7AALP_RFU_1A - 26 (length 0))
211+
0x208, // D7AALP_RFU_1B - 27 (length 0))
212+
0x214, // D7AALP_RFU_1C - 28 (length 0))
213+
0x220, // D7AALP_RFU_1D - 29 (length 0))
214+
0x22c, // D7AALP_RFU_1E - 30 (length 0))
215+
0x238, // D7AALP_RFU_1F - 31 (length 0))
216+
0x244, // ACCESS_PROFILE_0 - 32 (length 65))
217+
0x291, // ACCESS_PROFILE_1 - 33 (length 65))
218+
0x2de, // ACCESS_PROFILE_2 - 34 (length 65))
219+
0x32b, // ACCESS_PROFILE_3 - 35 (length 65))
220+
0x378, // ACCESS_PROFILE_4 - 36 (length 65))
221+
0x3c5, // ACCESS_PROFILE_5 - 37 (length 65))
222+
0x412, // ACCESS_PROFILE_6 - 38 (length 65))
223+
0x45f, // ACCESS_PROFILE_7 - 39 (length 65))
224+
0x4ac, // ACCESS_PROFILE_8 - 40 (length 65))
225+
0x4f9, // ACCESS_PROFILE_9 - 41 (length 65))
226+
0x546, // ACCESS_PROFILE_10 - 42 (length 65))
227+
0x593, // ACCESS_PROFILE_11 - 43 (length 65))
228+
0x5e0, // ACCESS_PROFILE_12 - 44 (length 65))
229+
0x62d, // ACCESS_PROFILE_13 - 45 (length 65))
230+
0x67a, // ACCESS_PROFILE_14 - 46 (length 65))
231+
//[[[end]]] (checksum: 042b6478cc347b741c10b6de3153b1d9)
232232
};
233233

234234
__attribute__((used)) uint8_t files_length[] = {
235235
/*[[[cog
236236
output_system_file_length()
237237
]]]*/
238238
0x14, // UID - 0)
239-
0x10, // FACTORY_SETTINGS - 1)
239+
0x19, // FACTORY_SETTINGS - 1)
240240
0x1b, // FIRMWARE_VERSION - 2)
241241
0x1f, // DEVICE_CAPACITY - 3)
242242
0x15, // DEVICE_STATUS - 4)
@@ -282,7 +282,7 @@ __attribute__((used)) uint8_t files_length[] = {
282282
0x4d, // ACCESS_PROFILE_12 - 44)
283283
0x4d, // ACCESS_PROFILE_13 - 45)
284284
0x4d, // ACCESS_PROFILE_14 - 46)
285-
//[[[end]]] (checksum: e84fba5d8d3ec166279358e4bea2f101)
285+
//[[[end]]] (checksum: bbc326f0152e2a522cb0548e2e8b11ad)
286286
};
287287

288288
__attribute__((used)) uint8_t d7ap_permanent_files_data[FRAMEWORK_FS_PERMANENT_STORAGE_SIZE] LINKER_SECTION_FS_SYSTEM_FILE = {
@@ -297,8 +297,8 @@ __attribute__((used)) uint8_t d7ap_permanent_files_data[FRAMEWORK_FS_PERMANENT_S
297297
0x24, 0x23, 0xff, 0xff, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0, 0x0, 0x8,
298298
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
299299
// FACTORY_SETTINGS - 1
300-
0x24, 0x23, 0xff, 0xff, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x4,
301-
0x0, 0x14, 0x11, 0x1,
300+
0x24, 0x23, 0xff, 0xff, 0x0, 0x0, 0x0, 0xd, 0x0, 0x0, 0x0, 0xd,
301+
0x0, 0x0, 0x0, 0x28, 0xe4, 0x0, 0x1, 0x33, 0x36, 0x0, 0x1, 0xeb, 0xac,
302302
// FIRMWARE_VERSION - 2
303303
0x24, 0x23, 0xff, 0xff, 0x0, 0x0, 0x0, 0xf, 0x0, 0x0, 0x0, 0xf,
304304
0x0, 0x0, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
@@ -434,7 +434,7 @@ __attribute__((used)) uint8_t d7ap_permanent_files_data[FRAMEWORK_FS_PERMANENT_S
434434
// ACCESS_PROFILE_14 - 46
435435
0x24, 0x23, 0xff, 0xff, 0x0, 0x0, 0x0, 0x41, 0x0, 0x0, 0x0, 0x41,
436436
0x32, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xe, 0x56, 0xff, 0x0, 0x0, 0x0, 0x0, 0xe, 0x56, 0xff, 0x0, 0x0, 0x0, 0x0, 0xe, 0x56, 0xff, 0x0, 0x0, 0x0, 0x0, 0xe, 0x56, 0xff, 0x0, 0x0, 0x0, 0x0, 0xe, 0x56, 0xff, 0x0, 0x0, 0x0, 0x0, 0xe, 0x56, 0xff, 0x0, 0x0, 0x0, 0x0, 0xe, 0x56, 0xff, 0x0, 0x0, 0x0, 0x0, 0xe, 0x56, 0xff,
437-
//[[[end]]] (checksum: 149f22e1928490f8553b2faf3cdef27a)
437+
//[[[end]]] (checksum: 3a946023cebf0bf007480483faf54484)
438438
};
439439

440440

‎stack/modules/d7ap/phy.c

Lines changed: 48 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,7 @@
4141

4242
#include "packet_queue.h"
4343
#include "MODULE_D7AP_defs.h"
44+
#include "d7ap_fs.h"
4445

4546
#if defined(FRAMEWORK_LOG_ENABLED) && defined(MODULE_D7AP_PHY_LOG_ENABLED)
4647
#define DPRINT(...) log_print_stack_string(LOG_STACK_PHY, __VA_ARGS__)
@@ -69,25 +70,28 @@
6970
#define BITRATE_L 9600 // bps
7071
#define FDEV_L 4800 // Hz
7172
// Carson's rule: 2 x fm + 2 x fd = 9.600 + 2 x 4.800 = 19.2 kHz
72-
// assuming 10 ppm crystals gives max error of: 2 * 10 ppm * 868 = 17.36 kHz
73-
// => BW > 19.2 + 17.36 kHz => > 36.5 kHZ.
74-
#define RXBW_L 36500 //Hz
73+
// assuming 1 ppm crystals gives max error of: 2 * 1 ppm * 868 = 1.736 kHz
74+
// => BW > 19.2 + 1.736 kHz => > 20.936 kHZ.
75+
// This results in 10.468 kHz on a single sideband.
76+
// #define RXBW_L 10468 //Hz
7577

7678
// normal rate
7779
#define BITRATE_N 55555 // bps
7880
#define FDEV_N 50000 // Hz
7981
// Carson's rule: 2 x fm + 2 x fd = 55.555 + 2 x 50 = 155.555 kHz
80-
// assuming 10 ppm crystals gives max error of: 2 * 10 ppm * 868 = 17.36 kHz
81-
// => BW > 155.555 + 17.36 => 172.91 KHz
82-
#define RXBW_N 172910 //Hz
82+
// assuming 1 ppm crystals gives max error of: 2 * 1 ppm * 868 = 1.736 kHz
83+
// => BW > 155.555 + 1.736 => 157.291 kHz.
84+
// This results in 78.646 kHz on a single sideband.
85+
// #define RXBW_N 78646 //Hz
8386

8487
// high rate
8588
#define BITRATE_H 166667 // bps
8689
#define FDEV_H 41667 // Hz
8790
// Carson's rule: 2 x fm + 2 x fd = 166.667 + 2 x 41.667 = 250 kHz
88-
// assuming 10 ppm crystals gives max error of: 2 * 10 ppm * 868 = 17.36 kHz
89-
// => BW > 250 + 17.36 kHz => > 267.36 kHZ.
90-
#define RXBW_H 267360 //Hz
91+
// assuming 1 ppm crystals gives max error of: 2 * 1 ppm * 868 = 1.736 kHz
92+
// => BW > 250 + 1.736 kHz => 251.736 kHz.
93+
// This results in 125.868 kHz on a single sideband.
94+
// #define RXBW_H 125868 //Hz
9195

9296
#define LORA_T_SYMBOL_SF9_MS 4.096 // based on SF9 and 125k BW
9397
#define LORA_T_PREAMBE_SF9_MS (8 + 4.25) * LORA_T_SYMBOL_SF9_MS // assuming 8 symbols for now
@@ -124,6 +128,13 @@ static channel_id_t default_channel_id = {
124128

125129
static channel_id_t current_channel_id = EMPTY_CHANNEL_ID;
126130

131+
static uint32_t rx_bw_lo_rate;
132+
static uint32_t rx_bw_normal_rate;
133+
static uint32_t rx_bw_hi_rate;
134+
static bool rx_bw_changed = false;
135+
136+
static uint8_t gain_offset = 0;
137+
127138
/*
128139
* FSK packet handler structure
129140
*/
@@ -360,16 +371,19 @@ uint16_t phy_calculate_tx_duration(phy_channel_class_t channel_class, phy_coding
360371

361372
static void configure_eirp(eirp_t eirp)
362373
{
363-
DPRINT("Set Tx power: %d dBm\n", eirp);
374+
eirp -= gain_offset;
375+
DPRINT("Set Tx power: %d dBm including offset of %i\n", eirp, gain_offset);
364376

365377
hw_radio_set_tx_power(eirp);
366378
}
367379

368380
static void configure_channel(const channel_id_t* channel) {
369-
if(phy_radio_channel_ids_equal(&current_channel_id, channel)) {
381+
if(phy_radio_channel_ids_equal(&current_channel_id, channel) && !rx_bw_changed) {
370382
return;
371383
}
372384

385+
rx_bw_changed = false;
386+
373387
// configure modulation settings
374388
if(channel->channel_header.ch_class == PHY_CLASS_LO_RATE)
375389
{
@@ -378,7 +392,7 @@ static void configure_channel(const channel_id_t* channel) {
378392
hw_radio_set_tx_fdev(FDEV_L);
379393
else
380394
hw_radio_set_tx_fdev(0);
381-
hw_radio_set_rx_bw_hz(RXBW_L);
395+
hw_radio_set_rx_bw_hz(rx_bw_lo_rate);
382396
hw_radio_set_preamble_size(PREAMBLE_LOW_RATE_CLASS * 8);
383397
}
384398
else if(channel->channel_header.ch_class == PHY_CLASS_NORMAL_RATE)
@@ -388,7 +402,7 @@ static void configure_channel(const channel_id_t* channel) {
388402
hw_radio_set_tx_fdev(FDEV_N);
389403
else
390404
hw_radio_set_tx_fdev(0);
391-
hw_radio_set_rx_bw_hz(RXBW_N);
405+
hw_radio_set_rx_bw_hz(rx_bw_normal_rate);
392406
hw_radio_set_preamble_size(PREAMBLE_NORMAL_RATE_CLASS * 8);
393407
}
394408
else if(channel->channel_header.ch_class == PHY_CLASS_HI_RATE)
@@ -398,7 +412,7 @@ static void configure_channel(const channel_id_t* channel) {
398412
hw_radio_set_tx_fdev(FDEV_H);
399413
else
400414
hw_radio_set_tx_fdev(0);
401-
hw_radio_set_rx_bw_hz(RXBW_H);
415+
hw_radio_set_rx_bw_hz(rx_bw_hi_rate);
402416
hw_radio_set_preamble_size(PREAMBLE_HI_RATE_CLASS * 8);
403417
}
404418

@@ -439,6 +453,22 @@ void continuous_tx_expiration()
439453
DPRINT("Continuous TX is now terminated");
440454
}
441455

456+
void fact_settings_file_change_callback()
457+
{
458+
uint8_t fact_settings[D7A_FILE_FACTORY_SETTINGS_SIZE];
459+
d7ap_fs_read_file(D7A_FILE_FACTORY_SETTINGS_FILE_ID, 0, fact_settings, D7A_FILE_FACTORY_SETTINGS_SIZE);
460+
461+
gain_offset = (int8_t)fact_settings[0];
462+
rx_bw_lo_rate = __builtin_bswap32(*((uint32_t*)(fact_settings+1)));
463+
rx_bw_normal_rate = __builtin_bswap32(*((uint32_t*)(fact_settings+5)));
464+
rx_bw_hi_rate = __builtin_bswap32(*((uint32_t*)(fact_settings+9)));
465+
466+
DPRINT("rx bw low rate is %i, normal rate is %i, high rate is %i\n", rx_bw_lo_rate, rx_bw_normal_rate, rx_bw_hi_rate);
467+
DPRINT("gain offset set to %i\n", gain_offset);
468+
469+
rx_bw_changed = true;
470+
}
471+
442472

443473
error_t phy_init(void) {
444474

@@ -465,6 +495,10 @@ error_t phy_init(void) {
465495
hw_radio_set_dc_free(HW_DC_FREE_NONE);
466496
#endif
467497

498+
fact_settings_file_change_callback();
499+
500+
fs_register_file_modified_callback(D7A_FILE_FACTORY_SETTINGS_FILE_ID, &fact_settings_file_change_callback);
501+
468502
configure_syncword(PHY_SYNCWORD_CLASS0, &default_channel_id);
469503
configure_channel(&default_channel_id);
470504
configure_eirp(10);

‎stack/modules/d7ap/phy.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -108,7 +108,7 @@ typedef struct
108108
*
109109
* This struct adheres to the 'Channel ID' format the Dash7 PHY layer. (@17/03/2015)
110110
*/
111-
typedef struct
111+
typedef struct __attribute__((__packed__))
112112
{
113113
union
114114
{

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