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Merge pull request #2404 from cesanta/g031
Add nucleo-g031 baremetal example
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‎examples/stm32/nucleo-g031-make-baremetal-builtin/Makefile

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CFLAGS = -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion
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CFLAGS += -Wformat-truncation -fno-common -Wconversion -Wno-sign-conversion
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CFLAGS += -g3 -O3 -ffunction-sections -fdata-sections
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CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_g0/Include
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CFLAGS += -mcpu=cortex-m0 -mthumb -mfloat-abi=soft $(CFLAGS_EXTRA)
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LDFLAGS ?= -Tlink.ld -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
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SOURCES = main.c syscalls.c mongoose.c
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SOURCES += cmsis_g0/Source/Templates/gcc/startup_stm32g031xx.s # ST startup file. Compiler-dependent!
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CFLAGS += -DHTTP_URL=\"http://0.0.0.0/\" # Example-specifig flags
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ifeq ($(OS),Windows_NT)
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RM = cmd /C del /Q /F /S
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else
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RM = rm -rf
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endif
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all build example: firmware.bin
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firmware.bin: firmware.elf
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arm-none-eabi-objcopy -O binary $< $@
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firmware.elf: cmsis_core cmsis_g0 $(SOURCES) hal.h link.ld Makefile mongoose_custom.h
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arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(LDFLAGS) -o $@
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flash: firmware.bin
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st-flash --reset write $< 0x8000000
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cmsis_core: # ARM CMSIS core headers
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git clone --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
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cmsis_g0: # ST CMSIS headers for STM32H5 series
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git clone --depth 1 -b v1.4.3 https://github.com/STMicroelectronics/cmsis_device_g0 $@
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# Automated remote test. Requires env variable VCON_API_KEY set. See https://vcon.io/automated-firmware-tests/
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DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/10
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update: firmware.bin
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curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$<
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test update: CFLAGS += -DUART_DEBUG=USART1
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test: update
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curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt
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grep 'READY, IP:' /tmp/output.txt # Check for network init
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clean:
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$(RM) firmware.* *.su cmsis_core cmsis_g0 mbedtls

‎examples/stm32/nucleo-g031-make-baremetal-builtin/hal.h

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// Copyright (c) 2022-2023 Cesanta Software Limited
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// All rights reserved
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//
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// MCU manual: RM0444, board manual: UM2591
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// https://www.st.com/resource/en/reference_manual/rm0444-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
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// https://www.st.com/resource/en/user_manual/um2591-stm32g0-nucleo32-board-mb1455-stmicroelectronics.pdf
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// Alternate functions: https://www.st.com/resource/en/datasheet/stm32g031c6.pdf
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#pragma once
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// #define LED PIN('B', 3)
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#define LED PIN('C', 6)
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#ifndef UART_DEBUG
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#define UART_DEBUG USART2
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#endif
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#include <stm32g031xx.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#define BIT(x) (1UL << (x))
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#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK)
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#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
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#define PINNO(pin) (pin & 255)
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#define PINBANK(pin) (pin >> 8)
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#define CPU_FREQUENCY 16000000
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#define AHB_FREQUENCY CPU_FREQUENCY
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#define APB_FREQUENCY CPU_FREQUENCY
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// #define APB1_FREQUENCY (AHB_FREQUENCY / (BIT(PPRE1 - 3)))
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static inline void spin(volatile uint32_t n) {
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while (n--) (void) 0;
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}
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enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG };
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enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
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enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_HIGH, GPIO_SPEED_INSANE };
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enum { GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN };
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#define GPIO(N) ((GPIO_TypeDef *) ((GPIOA_BASE) + 0x400 * (N)))
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static GPIO_TypeDef *gpio_bank(uint16_t pin) {
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return GPIO(PINBANK(pin));
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}
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static inline void gpio_toggle(uint16_t pin) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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uint32_t mask = BIT(PINNO(pin));
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gpio->BSRR = mask << (gpio->ODR & mask ? 16 : 0);
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}
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static inline int gpio_read(uint16_t pin) {
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return gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0;
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}
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static inline void gpio_write(uint16_t pin, bool val) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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gpio->BSRR = BIT(PINNO(pin)) << (val ? 0 : 16);
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}
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static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
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uint8_t speed, uint8_t pull, uint8_t af) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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uint8_t n = (uint8_t) (PINNO(pin));
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RCC->IOPENR |= BIT(PINBANK(pin)); // Enable GPIO clock
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SETBITS(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n);
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SETBITS(gpio->OSPEEDR, 3UL << (n * 2), ((uint32_t) speed) << (n * 2));
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SETBITS(gpio->PUPDR, 3UL << (n * 2), ((uint32_t) pull) << (n * 2));
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SETBITS(gpio->AFR[n >> 3], 15UL << ((n & 7) * 4),
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((uint32_t) af) << ((n & 7) * 4));
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SETBITS(gpio->MODER, 3UL << (n * 2), ((uint32_t) mode) << (n * 2));
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}
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static inline void gpio_input(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 0);
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}
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static inline void gpio_output(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 0);
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}
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static inline bool uart_init(USART_TypeDef *uart, unsigned long baud) {
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uint8_t af = 1; // Alternate function
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uint16_t rx = 0, tx = 0; // pins
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uint32_t freq = 0; // Bus frequency
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if (uart == USART1) {
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freq = CPU_FREQUENCY, RCC->APBENR2 |= RCC_APBENR2_USART1EN;
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tx = PIN('A', 9), rx = PIN('A', 10);
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} else if (uart == USART2) {
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freq = CPU_FREQUENCY, RCC->APBENR1 |= RCC_APBENR1_USART2EN;
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tx = PIN('A', 2), rx = PIN('A', 3);
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} else {
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return false;
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}
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gpio_init(tx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
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gpio_init(rx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
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uart->CR1 = 0; // Disable UART
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uart->BRR = freq / baud; // Set baud rate
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uart->CR1 = USART_CR1_RE | USART_CR1_TE; // Set mode to TX & RX
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uart->CR1 |= USART_CR1_UE; // Enable UART
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return true;
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}
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static inline void uart_write_byte(USART_TypeDef *uart, uint8_t byte) {
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uart->TDR = byte;
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while ((uart->ISR & BIT(7)) == 0) spin(1);
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}
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static inline void uart_write_buf(USART_TypeDef *uart, char *buf, size_t len) {
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while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
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}
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static inline int uart_read_ready(USART_TypeDef *uart) {
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return uart->ISR & BIT(5); // If RXNE bit is set, data is ready
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}
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static inline uint8_t uart_read_byte(USART_TypeDef *uart) {
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return (uint8_t) (uart->RDR & 255);
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}
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#ifndef RNG
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struct rng {
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volatile uint32_t CR, SR, DR;
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};
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#define RNG ((struct rng *) 0x40025000) // RM0444 2.2.2 Table 6
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#endif
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static inline void rng_init(void) {
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RCC->CCIPR |= 2U << 26U; // RNG clock source. Documented in 5.4.21
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RCC->AHBENR |= BIT(18); // RM0444 5.4.25 Table 36
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RNG->CR |= BIT(2); // 19.7.1
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}
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static inline uint32_t rng_read(void) {
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while ((RNG->SR & BIT(0)) == 0) (void) 0;
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return RNG->DR;
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}
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// Bit-bang SPI implementation
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struct spi {
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uint16_t miso, mosi, clk, cs; // Pins
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int spin; // Number of NOP spins for bitbanging
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};
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static inline void spi_begin(struct spi *spi) {
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gpio_write(spi->cs, 0);
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// printf("%s\n", __func__);
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}
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static inline void spi_end(struct spi *spi) {
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gpio_write(spi->cs, 1);
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// printf("%s\n", __func__);
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}
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static inline void spi_init(struct spi *spi) {
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gpio_input(spi->miso);
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gpio_output(spi->mosi);
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gpio_output(spi->clk);
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gpio_output(spi->cs);
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gpio_write(spi->cs, 1);
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// printf("%s\n", __func__);
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}
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// Send a byte, and return a received byte
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static inline uint8_t spi_txn(struct spi *spi, uint8_t write_byte) {
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unsigned count = spi->spin <= 0 ? 9 : (unsigned) spi->spin;
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uint8_t rx = 0, tx = write_byte;
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for (int i = 0; i < 8; i++) {
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gpio_write(spi->mosi, tx & 0x80U); // Set mosi
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gpio_write(spi->clk, 1); // Clock high
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spin(count); // Wait half cycle
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rx <<= 1U; // Shift alreay read bits
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if (gpio_read(spi->miso)) rx |= 1U; // Read next bit
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gpio_write(spi->clk, 0); // Clock low
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spin(count); // Wait half cycle
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tx <<= 1U; // Discard written bit
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}
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// printf("%s %02x %02x\n", __func__, (int) write_byte, (int) rx);
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return rx; // Return the received byte
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}
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#define UUID ((uint32_t *) UID_BASE) // Unique 96-bit chip ID. TRM 59.1
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// Helper macro for MAC generation, byte reads not allowed
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#define GENERATE_LOCALLY_ADMINISTERED_MAC() \
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{ \
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2, UUID[0] & 255, (UUID[0] >> 10) & 255, (UUID[0] >> 19) & 255, \
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UUID[1] & 255, UUID[2] & 255 \
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}

‎examples/stm32/nucleo-g031-make-baremetal-builtin/link.ld

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ENTRY(Reset_Handler);
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MEMORY {
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flash(rx) : ORIGIN = 0x08000000, LENGTH = 64k
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sram(rwx) : ORIGIN = 0x20000000, LENGTH = 8k
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}
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_estack = ORIGIN(sram) + LENGTH(sram); /* End of RAM. stack points here */
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SECTIONS {
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.vectors : { KEEP(*(.isr_vector)) } > flash
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.text : { *(.text* .text.*) } > flash
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.rodata : { *(.rodata*) } > flash
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.data : {
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_sdata = .;
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*(.first_data)
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*(.ram)
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*(.data SORT(.data.*))
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_edata = .;
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} > sram AT > flash
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_sidata = LOADADDR(.data);
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.bss : {
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_sbss = .;
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*(.bss SORT(.bss.*) COMMON)
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_ebss = .;
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} > sram
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. = ALIGN(8);
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_end = .;
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}

‎examples/stm32/nucleo-g031-make-baremetal-builtin/main.c

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// Copyright (c) 2023 Cesanta Software Limited
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// All rights reserved
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#include "hal.h"
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#include "mongoose.h"
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#define BLINK_PERIOD_MS 1000 // LED blinking period in millis
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static struct spi spi_pins = {
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.miso = PIN('B', 4),
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.mosi = PIN('A', 0),
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.clk = PIN('A', 1),
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.cs = PIN('A', 4),
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};
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uint32_t SystemCoreClock = CPU_FREQUENCY;
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void SystemInit(void) { // Called automatically by startup code
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rng_init();
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SysTick_Config(CPU_FREQUENCY / 1000); // Sys tick every 1ms
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}
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static volatile uint64_t s_ticks; // Milliseconds since boot
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void SysTick_Handler(void) { // SyStick IRQ handler, triggered every 1ms
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s_ticks++;
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}
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void mg_random(void *buf, size_t len) { // Use on-board RNG
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for (size_t n = 0; n < len; n += sizeof(uint32_t)) {
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uint32_t r = rng_read();
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memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r));
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}
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}
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uint64_t mg_millis(void) { // Let Mongoose use our uptime function
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return s_ticks; // Return number of milliseconds since boot
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}
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static void timer_fn(void *arg) {
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gpio_toggle(LED); // Blink LED
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struct mg_tcpip_if *ifp = arg; // And show
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MG_INFO(("Ethernet: %d, IP: %M, rx:%u, tx:%u, dr:%u, er:%u", ifp->state,
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mg_print_ip4, &ifp->ip, ifp->nrecv, ifp->nsent, ifp->ndrop,
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ifp->nerr));
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}
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static void fn(struct mg_connection *c, int ev, void *ev_data, void *fn_data) {
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struct mg_tcpip_if *ifp = (struct mg_tcpip_if *) fn_data;
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if (ev == MG_EV_HTTP_MSG) {
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struct mg_http_message *hm = (struct mg_http_message *) ev_data;
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if (mg_http_match_uri(hm, "/api/hello")) { // Request to /api/hello
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mg_http_reply(c, 200, "", "{%m:%u,%m:%u,%m:%u,%m:%u,%m:%u}\n",
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MG_ESC("eth"), ifp->state, MG_ESC("frames_received"),
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ifp->nrecv, MG_ESC("frames_sent"), ifp->nsent,
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MG_ESC("frames_dropped"), ifp->ndrop,
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MG_ESC("interface_errors"), ifp->nerr);
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} else if (mg_http_match_uri(hm, "/")) { // Index page
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mg_http_reply(
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c, 200, "", "%s",
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"<html><head><link rel='icon' href='data:;base64,='></head><body>"
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"<h1>Welcome to Mongoose</h1>"
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"See <a href=/api/hello>/api/hello</a> for REST example"
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"</body></html>");
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} else { // All other URIs
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mg_http_reply(c, 404, "", "Not Found\n");
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}
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}
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}
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int main(void) {
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gpio_output(LED); // Setup green LED
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uart_init(UART_DEBUG, 115200); // Initialise debug printf
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// ethernet_init(); // Initialise ethernet pins
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MG_INFO(("Starting, CPU freq %g MHz", (double) SystemCoreClock / 1000000));
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struct mg_mgr mgr; // Initialise
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mg_mgr_init(&mgr); // Mongoose event manager
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mg_log_set(MG_LL_DEBUG); // Set log level
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// Initialise Mongoose network stack
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spi_init(&spi_pins);
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struct mg_tcpip_spi spi = {
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.begin = (void (*)(void *)) spi_begin,
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.end = (void (*)(void *)) spi_end,
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.txn = (uint8_t(*)(void *, uint8_t)) spi_txn,
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.spi = &spi_pins,
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};
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struct mg_tcpip_if mif = {.mac = GENERATE_LOCALLY_ADMINISTERED_MAC(),
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// Uncomment below for static configuration:
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// .ip = mg_htonl(MG_U32(192, 168, 0, 223)),
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// .mask = mg_htonl(MG_U32(255, 255, 255, 0)),
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// .gw = mg_htonl(MG_U32(192, 168, 0, 1)),
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.driver = &mg_tcpip_driver_w5500,
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.driver_data = &spi};
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mg_tcpip_init(&mgr, &mif);
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MG_INFO(("MAC: %M. Waiting for IP...", mg_print_mac, mif.mac));
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while (mif.state != MG_TCPIP_STATE_READY) {
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mg_mgr_poll(&mgr, 0);
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}
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MG_INFO(("Initialising application..."));
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mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_fn, &mif);
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mg_http_listen(&mgr, "http://0.0.0.0:80", fn, &mif);
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MG_INFO(("Starting event loop"));
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for (;;) {
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mg_mgr_poll(&mgr, 0);
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}
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return 0;
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}

‎examples/stm32/nucleo-g031-make-baremetal-builtin/mongoose.c

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../../../mongoose.c

‎examples/stm32/nucleo-g031-make-baremetal-builtin/mongoose.h

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../../../mongoose.h

‎examples/stm32/nucleo-g031-make-baremetal-builtin/mongoose_custom.h

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#pragma once
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#define MG_ARCH MG_ARCH_NEWLIB
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#define MG_ENABLE_TCPIP 1
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#define MG_ENABLE_CUSTOM_MILLIS 1
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#define MG_ENABLE_CUSTOM_RANDOM 1
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#define MG_IO_SIZE 128
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#define MG_ENABLE_LINES 1

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