feat: add stm32h7 port

Signed-off-by: sakumisu <1203593632@qq.com>

Author: sakumisu

CMakeLists.txt

@@ -31,6 +31,10 @@ if(CONFIG_CHERRYECAT)
         endif()
     endif()
 
+    if(CHERRYECAT_NETDEV_STM32H7)
+        list(APPEND cherryec_srcs port/netdev_stm32h7.c)
+    endif()
+
     if(HPM_SDK_BASE)
         list(APPEND cherryec_srcs port/netdev_hpmicro.c)
         sdk_inc(${cherryec_incs})

README.md

@@ -109,6 +109,8 @@ Generating C code...
 
 - HPM6750EVK2/HPM6800EVK/**HPM5E00EVK**(hybrid internal)
 - RT-Thread RZN2L-EtherKit/RA8P1 Titan/RuiQing Pai
+- STM32H7
+
 
 ## Contact
 

README_zh.md

@@ -109,6 +109,7 @@ Generating C code...
 
 - HPM6750EVK2/HPM6800EVK/**HPM5E00EVK**(hybrid internal)
 - RT-Thread RZN2L-EtherKit/RA8P1 Titan/RuiQing Pai
+- STM32H7
 
 ## 联系
 

SConscript

@@ -31,6 +31,9 @@ if GetDepend(['PKG_CHERRYECAT_NETDEV_HPMICRO']):
 if GetDepend(['PKG_CHERRYECAT_NETDEV_RENESAS']):
     src += Glob('port/netdev_renesas.c')
 
+if GetDepend(['PKG_CHERRYECAT_NETDEV_STM32H7']):
+    src += Glob('port/netdev_stm32h7.c')
+
 group = DefineGroup('CherryECAT', src, depend = ['PKG_USING_CHERRYECAT'], LIBS = LIBS, LIBPATH=LIBPATH, CPPPATH = path, CPPDEFINES = CPPDEFINES)
 
 Return('group')

demo/stm32h7/README.md

@@ -0,0 +1,92 @@
+# CherryECAT STM32
+
+Use ``git clone https://github.com/sakumisu/cherryecat_stm32h7.git --recursive``
+
+**Please do not modify main.c and xxx_it.c when generating code with cubemx.**
+
+## Caution
+
+- Must enable `USE_HAL_TIM_REGISTER_CALLBACKS to 1 in stm32h7xx_hal_conf.h`
+- STM32H7 HAL version must >= 1.11.x
+- Must modify sct file for `RxDescripSection`, `TxDescripSection` and `TRx_PoolSection`
+
+```
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00200000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00200000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+  RW_IRAM2 0x24000000 0x00080000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+   RW_DMARxDscrTab 0x30000000 0x80 {
+  *(.RxDescripSection)
+  }
+  RW_DMATxDscrTab 0x30000080 0x80 {
+  *(.TxDescripSection)
+  }
+  memory_TRX_POOL_base 0x30000100 0x3F00 {
+  *(.TRx_PoolSection)
+  }
+
+}
+
+```
+
+- Must config mpu with nocache for 0x30000000 base
+
+```
+void MPU_Config(void)
+{
+  MPU_Region_InitTypeDef MPU_InitStruct = {0};
+
+  /* Disables the MPU */
+  HAL_MPU_Disable();
+
+  /** Initializes and configures the Region and the memory to be protected
+  */
+  MPU_InitStruct.Enable = MPU_REGION_ENABLE;
+  MPU_InitStruct.Number = MPU_REGION_NUMBER0;
+  MPU_InitStruct.BaseAddress = 0x0;
+  MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
+  MPU_InitStruct.SubRegionDisable = 0x87;
+  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
+  MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
+  MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
+  MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
+  MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
+  MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
+
+  HAL_MPU_ConfigRegion(&MPU_InitStruct);
+
+  /** Initializes and configures the Region and the memory to be protected
+  */
+  MPU_InitStruct.Number = MPU_REGION_NUMBER1;
+  MPU_InitStruct.BaseAddress = 0x30000000;
+  MPU_InitStruct.Size = MPU_REGION_SIZE_256B;
+  MPU_InitStruct.SubRegionDisable = 0x0;
+  MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
+  MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
+  MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
+  MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
+
+  HAL_MPU_ConfigRegion(&MPU_InitStruct);
+  /* Enables the MPU */
+  HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
+
+}
+```
+
+- Must add PHY_RESET macro in ec_config.h
+
+```
+#define CONFIG_EC_PHY_RESET_PORT 0 // 0 for GPIOA
+#define CONFIG_EC_PHY_RESET_PIN 8
+
+```