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[cd] Bump CIRCT from firtool-1.96.0 to firtool-1.97.1 (#4553)
* [cd] Bump CIRCT from firtool-1.96.0 to firtool-1.97.1 This is an automated commit generated by the `circt/update-circt` GitHub Action. * [test] Add Verilog test of inline emission, NFC Add an integration test of SystemVerilog generation for inline layers. This relies on new support in firtool 1.97.0 which adds support for compiling this feature. Previous versions of firtool could parse inline layers, but error when compiling them. * [test] Switch to new inline layer ABI (#4550) Change `LayerSpec` to use the new inline layer ABI. This uses '$' as a delimiter instead of '_' in order to avoid ambiguity related to layer names which may contain '_'. This now also includes the circuit name and a leading 'layer_'. * [test] Update btor2 emission test There was a change in the btor2 emission upstream. Update the test to match the new emission. I did not validate the correctness of this change. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: chiselbot <chiselbot@users.noreply.github.com>
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‎etc/circt.json

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@@ -1,3 +1,3 @@
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{
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"version": "firtool-1.96.0"
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"version": "firtool-1.97.1"
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}

‎src/test/scala/chiselTests/LayerSpec.scala

Lines changed: 43 additions & 7 deletions
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@@ -5,6 +5,7 @@ package chiselTests
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import chisel3._
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import chisel3.experimental.hierarchy.core.{Definition, Instance}
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import chisel3.experimental.hierarchy.instantiable
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import chisel3.ltl.AssertProperty
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import chisel3.probe.{define, Probe, ProbeValue}
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import chiselTests.{ChiselFlatSpec, FileCheck, Utils}
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import java.nio.file.{FileSystems, Paths}
@@ -380,25 +381,60 @@ class LayerSpec extends ChiselFlatSpec with Utils with FileCheck {
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)
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}
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"Inline layers" should "generated expected FIRRTL" in {
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object A extends layer.Layer(layer.LayerConfig.Inline) {
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object B extends layer.Layer(layer.LayerConfig.Inline)
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"Inline layers" should "generate expected FIRRTL and SystemVerilog" in {
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object A extends layer.Layer(layer.LayerConfig.Extract()) {
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object B extends layer.Layer(layer.LayerConfig.Inline) {
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object C extends layer.Layer(layer.LayerConfig.Inline)
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}
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}
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class Foo extends RawModule {
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class Foo extends Module {
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val a = IO(Input(UInt(2.W)))
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layer.block(A) {
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layer.block(A.B) {}
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AssertProperty(a > 0.U, "foo")
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layer.block(A.B) {
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AssertProperty(a > 1.U, "bar")
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layer.block(A.B.C) {
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AssertProperty(a > 2.U, "baz")
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}
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}
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}
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}
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info("FIRRTL okay")
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generateFirrtlAndFileCheck(new Foo) {
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"""|CHECK: layer A, inline :
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"""|CHECK: layer A, bind
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|CHECK-NEXT: layer B, inline :
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|CHECK-NEXT: layer C, inline :
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|""".stripMargin
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}
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info("SystemVerilog okay")
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val verilog = ChiselStage.emitSystemVerilog(
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new Foo,
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firtoolOpts = Array(
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"-disable-all-randomization",
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"-enable-layers=Verification,Verification.Assert,Verification.Assume,Verification.Cover"
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)
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)
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fileCheckString(verilog) {
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"""|CHECK: module Foo(
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|CHECK-NOT: assert property
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|
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|CHECK: module Foo_A(
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|CHECK-NOT: `ifdef
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|CHECK: foo: assert property
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|CHECK: `ifdef layer_Foo$A$B
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|CHECK-NEXT: bar: assert property
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|CHECK-NEXT: `ifdef layer_Foo$A$B$C
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|CHECK-NEXT: baz: assert property
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|CHECK-NEXT: `endif
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|CHECK-NEXT: `endif""".stripMargin
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}
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}
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"Inline layers" should "be ignored when choosing default output directories" in {
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they should "be ignored when choosing default output directories" in {
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object LayerWithDefaultOutputDir extends layer.Layer(layer.LayerConfig.Extract()) {
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object InlineSublayer extends layer.Layer(layer.LayerConfig.Inline) {
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object SublayerWithDefaultOutputDir extends layer.Layer(layer.LayerConfig.Extract()) {}

‎src/test/scala/circtTests/stage/ChiselStageSpec.scala

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Original file line numberDiff line numberDiff line change
@@ -1200,31 +1200,31 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.Utils {
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new Counter,
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firtoolOpts = Array("-enable-layers=Verification,Verification.Assert,Verification.Assume,Verification.Cover")
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)
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btor2 should include("""1 sort bitvec 1
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|2 input 1 reset
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|3 sort bitvec 32
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|4 state 3 count
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|5 state 1 hbr
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|6 constd 1 0
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|7 init 1 5 6
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|8 constd 3 43
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|9 constd 3 1
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|10 constd 3 42
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|11 constd 3 0
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|12 eq 1 4 10
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|13 add 3 4 9
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|14 ite 3 12 11 13
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|15 ult 1 4 8
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|16 constd 1 -1
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|17 or 1 2 5
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|18 xor 1 2 16
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|19 and 1 5 18
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|20 implies 1 19 15
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|21 not 1 20
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|22 bad 21
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|23 ite 3 2 11 14
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|24 next 3 4 23
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|25 next 1 5 17""".stripMargin)
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btor2 should include("""|1 sort bitvec 1
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|2 input 1 reset
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|3 sort bitvec 32
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|4 state 3 count
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|5 constd 1 0
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|6 state 1 hbr
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|7 init 1 6 5
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|8 constd 3 43
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|9 constd 3 1
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|10 constd 3 42
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|11 constd 3 0
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|12 eq 1 4 10
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|13 add 3 4 9
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|14 ite 3 12 11 13
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|15 ult 1 4 8
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|16 constd 1 -1
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|17 or 1 2 6
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|18 xor 1 2 16
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|19 and 1 6 18
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|20 implies 1 19 15
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|21 not 1 20
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|22 bad 21
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|23 ite 3 2 11 14
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|24 next 3 4 23
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|25 next 1 6 17""".stripMargin)
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}
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it("""should error if give a "--target-directory" option""") {

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