Discussions

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  Can an ExtModule be tested with ChiselSim?

  orpheezt asked Mar 3, 2026 in Q&A · Closed · Unanswered

  

  

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  Intellij "cannot resolve symbol" errors

  kazutomo started Feb 23, 2026 in General

  

  

  

  

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  Chisel 7.0.0-RC1 and Intellij errors

  kazutomo asked May 9, 2025 in Q&A · Closed · Unanswered

  

  

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  Chisel's Migration Progress and Plans for Scala 3

  Emin017 asked Nov 25, 2025 in Q&A · Answered

  

  

  

  

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  [Enhancement] Integrate NVIDIA GEM for 5-40x Faster RTL Simulation in ChiselSim

  csbohan started Jan 9, 2026 in Ideas

  

  

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  ChiselSim: Enable caching of elaborated modules

  gdnmhr asked Dec 18, 2025 in Q&A · Unanswered

  

  

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  Disabling warnings from C++ compiler in ChiselSim tests?

  oharboe started Dec 15, 2025 in General

  

  

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  Addressing svsim dependency inversion w.r.t. build systems

  oharboe started Dec 9, 2025 in General

  

  

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  Can I run the build of tests in bazel?

  oharboe started Oct 21, 2025 in General

  

  

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  Can I run .fir generation in parallel?

  oharboe started Oct 21, 2025 in General

  

  

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  怎么书写批量的条件选择when的块，使得生成的verilog不是一个个独立的if块而是if-else串(Translated:How to structure Chisel's when blocks to generate if-else cascades in Verilog rather than discrete if statements.)

  msuadOf asked Sep 18, 2025 in Q&A · Unanswered

  

  

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  DataView mapping for UInt -> ChiselEnum

  phelixmw started Aug 21, 2025 in Ideas

  

  

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  How can I map DataView to signal names with suffices?

  phelixmw asked Aug 11, 2025 in Q&A · Unanswered

  

  

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  Tip when running out of memory creating ROMs in peek-poke less tests

  oharboe started Aug 2, 2025 in General

  

  

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  Passing options to firtool in Chisel tests

  oharboe started Aug 2, 2025 in General

  

  

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  printf problems with Chisel 7.0.0-RC3:

  oharboe started Aug 1, 2025 in General

  

  

  

  

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  Chisel 7.0.0 error from testbench in Verilator

  oharboe started Jul 29, 2025 in General

  

  

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  Is there an idiomatic way in Chisel to display enum as ascii in .vcd files?

  oharboe started Jul 28, 2025 in General

  

  

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  A friendly name for VecInit() in .sv?

  oharboe started Jul 27, 2025 in General

  

  

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  Can I get the name of a test?

  oharboe started Jul 22, 2025 in General

  

  

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  Unexpected message: Ready

  oharboe started Jul 23, 2025 in General

  

  

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  How to emit vcd file when using chisel3.simulator for testing?

  longfangsong asked Mar 30, 2024 in Q&A · Answered

  

  

  

  

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  does Chisel have any property matching "final" in SV?

  phelixmw asked May 5, 2025 in Q&A · Unanswered

  

  

  

  

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  Will Chisel add support for Scala3 ? (Chisel是否会加入对Scala3的支持?)

  SDTEFU asked Jan 13, 2023 in Q&A · Unanswered

  

  

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  ChiselSim status

  iamavolk asked Apr 30, 2024 in Q&A · Unanswered

  

  

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