systemverilog-plugin: set range before range_valid

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>

Author: kamilrakoczy

systemverilog-plugin/UhdmAst.cc

@@ -511,6 +511,8 @@ static void convert_packed_unpacked_range(AST::AstNode *wire_node)
     if (packed_ranges.empty() && unpacked_ranges.empty()) {
         wire_node->attributes.erase(UhdmAst::packed_ranges());
         wire_node->attributes.erase(UhdmAst::unpacked_ranges());
+        wire_node->range_left = 0;
+        wire_node->range_right = 0;
         wire_node->range_valid = true;
         return;
     }