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kamilrakoczykamilrakoczy
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Merge pull request #466 from antmicro/kr/process_module
systemverilog-plugin: update module parameters processing
2 parents 24755e3 + 0c7f1c0 commit e0a923c

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‎systemverilog-plugin/UhdmAst.cc

Lines changed: 28 additions & 66 deletions
Original file line numberDiff line numberDiff line change
@@ -1902,53 +1902,44 @@ void UhdmAst::process_module()
19021902
} else {
19031903
// Not a top module, create instance
19041904
current_node = make_ast_node(AST::AST_CELL);
1905-
std::string module_parameters;
1905+
std::vector<std::pair<RTLIL::IdString, RTLIL::Const>> parameters;
19061906
visit_one_to_many({vpiParamAssign}, obj_h, [&](AST::AstNode *node) {
19071907
if (node && node->type == AST::AST_PARAMETER) {
1908+
log_assert(!node->children.empty());
19081909
if (node->children[0]->type != AST::AST_CONSTANT) {
19091910
if (shared.top_nodes.count(type)) {
19101911
simplify_parameter(node, shared.top_nodes[type]);
1911-
log_assert(node->children[0]->type == AST::AST_CONSTANT || node->children[0]->type == AST::AST_REALVALUE);
1912+
} else {
1913+
simplify_parameter(node, nullptr);
19121914
}
19131915
}
1914-
if (shared.top_nodes.count(type)) {
1915-
if (!node->children[0]->str.empty())
1916-
module_parameters += node->str + "=" + node->children[0]->str;
1917-
else
1918-
module_parameters +=
1919-
node->str + "=" + std::to_string(node->children[0]->bits.size()) + "'d" + std::to_string(node->children[0]->integer);
1920-
}
1916+
log_assert(node->children[0]->type == AST::AST_CONSTANT || node->children[0]->type == AST::AST_REALVALUE);
1917+
parameters.push_back(std::make_pair(node->str, node->children[0]->asParaConst()));
19211918
delete node;
19221919
}
19231920
});
1924-
// rename module in same way yosys do
1925-
std::string module_name;
1926-
if (module_parameters.size() > 60)
1927-
module_name = "$paramod$" + sha1(module_parameters) + type;
1928-
else if (!module_parameters.empty())
1929-
module_name = "$paramod" + type + module_parameters;
1930-
else
1931-
module_name = type;
1921+
// We need to rename module to prevent name collision with the same module, but with different parameters
1922+
std::string module_name = !parameters.empty() ? AST::derived_module_name(type, parameters).c_str() : type;
19321923
auto module_node = shared.top_nodes[module_name];
1933-
auto cell_instance = vpi_get(vpiCellInstance, obj_h);
1924+
// true, when Surelog don't have definition of module while parsing design
1925+
// if so, we leaving module parameters to yosys and don't rename module
1926+
// as it will be done by yosys
1927+
bool isPrimitive = false;
19341928
if (!module_node) {
19351929
module_node = shared.top_nodes[type];
19361930
if (!module_node) {
19371931
module_node = new AST::AstNode(AST::AST_MODULE);
19381932
module_node->str = type;
19391933
module_node->attributes[UhdmAst::partial()] = AST::AstNode::mkconst_int(2, false, 1);
1940-
cell_instance = 1;
1941-
module_name = type;
1934+
module_node->attributes[ID::whitebox] = AST::AstNode::mkconst_int(1, false, 1);
19421935
}
1943-
if (!module_parameters.empty()) {
1936+
isPrimitive = module_node->attributes.count(UhdmAst::partial()) && module_node->attributes[UhdmAst::partial()]->integer == 2;
1937+
if (!parameters.empty() && !isPrimitive) {
19441938
module_node = module_node->clone();
1939+
module_node->str = module_name;
19451940
}
19461941
}
1947-
module_node->str = module_name;
19481942
shared.top_nodes[module_node->str] = module_node;
1949-
if (cell_instance) {
1950-
module_node->attributes[ID::whitebox] = AST::AstNode::mkconst_int(1, false, 1);
1951-
}
19521943
visit_one_to_many({vpiParamAssign}, obj_h, [&](AST::AstNode *node) {
19531944
if (node) {
19541945
if (node->children[0]->type != AST::AST_CONSTANT) {
@@ -1957,39 +1948,14 @@ void UhdmAst::process_module()
19571948
log_assert(node->children[0]->type == AST::AST_CONSTANT || node->children[0]->type == AST::AST_REALVALUE);
19581949
}
19591950
}
1960-
auto parent_node = std::find_if(module_node->children.begin(), module_node->children.end(), [&](AST::AstNode *child) -> bool {
1961-
return ((child->type == AST::AST_PARAMETER) || (child->type == AST::AST_LOCALPARAM)) && child->str == node->str &&
1962-
// skip real parameters as they are currently not working: https://github.com/alainmarcel/Surelog/issues/1035
1963-
child->type != AST::AST_REALVALUE;
1964-
});
1965-
if (parent_node != module_node->children.end()) {
1966-
if ((*parent_node)->type == AST::AST_PARAMETER) {
1967-
if (cell_instance ||
1968-
(!node->children.empty() &&
1969-
node->children[0]->type !=
1970-
AST::AST_CONSTANT)) { // if cell is a blackbox or we need to simplify parameter first, left setting parameters to yosys
1971-
// We only want to add AST_PARASET for parameters that is different than already set
1972-
// to match the name yosys gives to the module.
1973-
// Note: this should also be applied for other (not only cell_instance) modules
1974-
// but as we are using part of the modules parsed by sv2v and other
1975-
// part by uhdm, we need to always rename module if it is parametrized,
1976-
// Otherwise, verilog frontend can use module parsed by uhdm and try to set
1977-
// parameters, but this module would be already parametrized
1978-
if ((node->children[0]->integer != (*parent_node)->children[0]->integer ||
1979-
node->children[0]->str != (*parent_node)->children[0]->str)) {
1980-
node->type = AST::AST_PARASET;
1981-
current_node->children.push_back(node);
1982-
}
1983-
} else {
1984-
add_or_replace_child(module_node, node);
1985-
}
1986-
} else {
1987-
add_or_replace_child(module_node, node);
1988-
}
1989-
} else if ((module_node->attributes.count(UhdmAst::partial()) && module_node->attributes[UhdmAst::partial()]->integer == 2)) {
1990-
// When module definition is not parsed by Surelog, left setting parameters to yosys
1951+
// if module is primitive
1952+
// Surelog doesn't have definition of this module,
1953+
// so we need to left setting of parameters to yosys
1954+
if (isPrimitive) {
19911955
node->type = AST::AST_PARASET;
19921956
current_node->children.push_back(node);
1957+
} else {
1958+
add_or_replace_child(module_node, node);
19931959
}
19941960
}
19951961
});
@@ -2006,16 +1972,12 @@ void UhdmAst::process_module()
20061972
current_node->children.insert(current_node->children.begin(), typeNode);
20071973
auto old_top = shared.current_top_node;
20081974
shared.current_top_node = module_node;
2009-
visit_one_to_many({vpiVariables, vpiNet, vpiArrayNet}, obj_h, [&](AST::AstNode *node) {
2010-
if (node) {
2011-
add_or_replace_child(module_node, node);
2012-
}
2013-
});
2014-
visit_one_to_many({vpiInterface, vpiModule, vpiPort, vpiGenScopeArray, vpiContAssign, vpiTaskFunc}, obj_h, [&](AST::AstNode *node) {
2015-
if (node) {
2016-
add_or_replace_child(module_node, node);
2017-
}
2018-
});
1975+
visit_one_to_many({vpiVariables, vpiNet, vpiArrayNet, vpiInterface, vpiModule, vpiPort, vpiGenScopeArray, vpiContAssign, vpiTaskFunc}, obj_h,
1976+
[&](AST::AstNode *node) {
1977+
if (node) {
1978+
add_or_replace_child(module_node, node);
1979+
}
1980+
});
20191981
make_cell(obj_h, current_node, module_node);
20201982
shared.current_top_node = old_top;
20211983
}

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