@@ -51,6 +51,15 @@ namespace systemverilog_plugin
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using namespace ::Yosys;
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using namespace ::Yosys::AST_INTERNAL;
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+
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+ void detect_sign_width_proxy (Yosys::AST::AstNode * node, int & width, bool & sign, bool *found_real = NULL ) {
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+ if (node->type == Yosys::AST::AST_IDENTIFIER && node->id2ast && node->id2ast ->type == Yosys::AST::AST_TYPEDEF) {
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+ node->id2ast ->dumpAst (nullptr , " ---------" );
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+ node->id2ast = node->id2ast ->children [0 ];
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+ }
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+ node->detectSignWidth (width, sign, found_real);
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+ }
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+
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void annotateTypedEnums (Yosys::AST::AstNode *ast_node, Yosys::AST::AstNode *template_node)
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{
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// check if enum
@@ -1036,8 +1045,8 @@ bool simplify(Yosys::AST::AstNode *ast_node, bool const_fold, bool at_zero, bool
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did_something = true ;
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while (!ast_node->children [1 ]->basic_prep && simplify (ast_node->children [1 ], false , false , false , stage, -1 , false , in_param) == true )
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did_something = true ;
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- ast_node->children [0 ]-> detectSignWidth ( backup_width_hint, backup_sign_hint);
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- ast_node->children [1 ]-> detectSignWidth ( width_hint, sign_hint);
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+ detect_sign_width_proxy ( ast_node->children [0 ], backup_width_hint, backup_sign_hint);
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+ detect_sign_width_proxy ( ast_node->children [1 ], width_hint, sign_hint);
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width_hint = max (width_hint, backup_width_hint);
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child_0_is_self_determined = true ;
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// test only once, before optimizations and memory mappings but after assignment LHS was mapped to an identifier
@@ -1117,7 +1126,7 @@ bool simplify(Yosys::AST::AstNode *ast_node, bool const_fold, bool at_zero, bool
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}
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while (!ast_node->children [0 ]->basic_prep && simplify (ast_node->children [0 ], false , false , false , stage, -1 , false , true ) == true )
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did_something = true ;
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- ast_node->children [0 ]-> detectSignWidth ( width_hint, sign_hint);
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+ detect_sign_width_proxy ( ast_node->children [0 ], width_hint, sign_hint);
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if (ast_node->children .size () > 1 && ast_node->children [1 ]->type == Yosys::AST::AST_RANGE) {
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while (!ast_node->children [1 ]->basic_prep && simplify (ast_node->children [1 ], false , false , false , stage, -1 , false , true ) == true )
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did_something = true ;
@@ -1129,7 +1138,7 @@ bool simplify(Yosys::AST::AstNode *ast_node, bool const_fold, bool at_zero, bool
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case Yosys::AST::AST_ENUM_ITEM:
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while (!ast_node->children [0 ]->basic_prep && simplify (ast_node->children [0 ], false , false , false , stage, -1 , false , in_param))
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did_something = true ;
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- ast_node->children [0 ]-> detectSignWidth ( width_hint, sign_hint);
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+ detect_sign_width_proxy ( ast_node->children [0 ], width_hint, sign_hint);
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if (ast_node->children .size () > 1 && ast_node->children [1 ]->type == Yosys::AST::AST_RANGE) {
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while (!ast_node->children [1 ]->basic_prep && simplify (ast_node->children [1 ], false , false , false , stage, -1 , false , in_param))
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did_something = true ;
@@ -1230,11 +1239,11 @@ bool simplify(Yosys::AST::AstNode *ast_node, bool const_fold, bool at_zero, bool
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for (auto child : ast_node->children )
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while (!child->basic_prep && simplify (child, false , false , in_lvalue, stage, -1 , false , in_param) == true )
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did_something = true ;
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- ast_node-> detectSignWidth ( width_hint, sign_hint);
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+ detect_sign_width_proxy (ast_node, width_hint, sign_hint);
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}
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if (ast_node->type == Yosys::AST::AST_FCALL && ast_node->str == " \\ $past" )
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- ast_node-> detectSignWidth ( width_hint, sign_hint);
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+ detect_sign_width_proxy (ast_node, width_hint, sign_hint);
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if (ast_node->type == Yosys::AST::AST_TERNARY) {
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if (width_hint < 0 ) {
@@ -1253,13 +1262,13 @@ bool simplify(Yosys::AST::AstNode *ast_node, bool const_fold, bool at_zero, bool
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did_something = true ;
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unevaluated_tern_branch = backup_unevaluated_tern_branch;
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- ast_node-> detectSignWidth ( width_hint, sign_hint);
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+ detect_sign_width_proxy (ast_node, width_hint, sign_hint);
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}
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int width_hint_left, width_hint_right;
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bool sign_hint_left, sign_hint_right;
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bool found_real_left, found_real_right;
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- ast_node->children [1 ]-> detectSignWidth ( width_hint_left, sign_hint_left, &found_real_left);
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- ast_node->children [2 ]-> detectSignWidth ( width_hint_right, sign_hint_right, &found_real_right);
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+ detect_sign_width_proxy ( ast_node->children [1 ], width_hint_left, sign_hint_left, &found_real_left);
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+ detect_sign_width_proxy ( ast_node->children [2 ], width_hint_right, sign_hint_right, &found_real_right);
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if (found_real_left || found_real_right) {
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child_1_is_self_determined = true ;
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child_2_is_self_determined = true ;
@@ -1280,7 +1289,7 @@ bool simplify(Yosys::AST::AstNode *ast_node, bool const_fold, bool at_zero, bool
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if (const_fold && ast_node->type == Yosys::AST::AST_CASE)
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{
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- ast_node-> detectSignWidth ( width_hint, sign_hint);
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+ detect_sign_width_proxy (ast_node, width_hint, sign_hint);
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while (simplify (ast_node->children [0 ], const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) { }
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if (ast_node->children [0 ]->type == Yosys::AST::AST_CONSTANT && ast_node->children [0 ]->bits_only_01 ()) {
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ast_node->children [0 ]->is_signed = sign_hint;
@@ -1415,7 +1424,7 @@ bool simplify(Yosys::AST::AstNode *ast_node, bool const_fold, bool at_zero, bool
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width_hint = backup_width_hint;
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sign_hint = backup_sign_hint;
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if (width_hint < 0 )
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- ast_node-> detectSignWidth ( width_hint, sign_hint);
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+ detect_sign_width_proxy (ast_node, width_hint, sign_hint);
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}
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current_block = backup_current_block;
@@ -1994,7 +2003,7 @@ bool simplify(Yosys::AST::AstNode *ast_node, bool const_fold, bool at_zero, bool
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{
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int expr_width_hint = -1 ;
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bool expr_sign_hint = true ;
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- varbuf-> detectSignWidth ( expr_width_hint, expr_sign_hint);
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+ detect_sign_width_proxy (varbuf, expr_width_hint, expr_sign_hint);
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while (simplify (varbuf, true , false , false , stage, 32 , true , false )) { }
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}
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@@ -2035,7 +2044,7 @@ bool simplify(Yosys::AST::AstNode *ast_node, bool const_fold, bool at_zero, bool
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{
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int expr_width_hint = -1 ;
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bool expr_sign_hint = true ;
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- buf-> detectSignWidth ( expr_width_hint, expr_sign_hint);
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+ detect_sign_width_proxy (buf, expr_width_hint, expr_sign_hint);
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while (simplify (buf, true , false , false , stage, expr_width_hint, expr_sign_hint, false )) { }
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}
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@@ -2086,7 +2095,7 @@ bool simplify(Yosys::AST::AstNode *ast_node, bool const_fold, bool at_zero, bool
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{
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int expr_width_hint = -1 ;
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bool expr_sign_hint = true ;
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- buf-> detectSignWidth ( expr_width_hint, expr_sign_hint);
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+ detect_sign_width_proxy (buf, expr_width_hint, expr_sign_hint);
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while (simplify (buf, true , false , false , stage, expr_width_hint, expr_sign_hint, true )) { }
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}
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@@ -2500,7 +2509,7 @@ bool simplify(Yosys::AST::AstNode *ast_node, bool const_fold, bool at_zero, bool
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int shamt_width_hint = -1 ;
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bool shamt_sign_hint = true ;
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- shift_expr-> detectSignWidth ( shamt_width_hint, shamt_sign_hint);
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+ detect_sign_width_proxy (shift_expr, shamt_width_hint, shamt_sign_hint);
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Yosys::AST::AstNode *wire_sel = new Yosys::AST::AstNode (Yosys::AST::AST_WIRE, new Yosys::AST::AstNode (Yosys::AST::AST_RANGE, ast_node->mkconst_int (shamt_width_hint-1 , true ), ast_node->mkconst_int (0 , true )));
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wire_sel->str = stringf (" $bitselwrite$sel$%s:%d$%d" , encode_filename (ast_node->filename ).c_str (), ast_node->location .first_line , autoidx++);
@@ -2709,7 +2718,7 @@ skip_dynamic_range_lvalue_expansion:;
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{
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int child_width_hint = -1 ;
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bool child_sign_hint = true ;
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- child-> detectSignWidth ( child_width_hint, child_sign_hint);
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+ detect_sign_width_proxy (child, child_width_hint, child_sign_hint);
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Yosys::AST::AstNode *rhs = wire_tmp_id->clone ();
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rhs->children .push_back (new Yosys::AST::AstNode (Yosys::AST::AST_RANGE, ast_node->mkconst_int (cursor+child_width_hint-1 , true ), ast_node->mkconst_int (cursor, true )));
@@ -3128,12 +3137,12 @@ skip_dynamic_range_lvalue_expansion:;
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// Is this needed?
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// while (simplify(buf, true, false, false, stage, width_hint, sign_hint, false)) { }
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- if (buf->type == Yosys::AST::AST_IDENTIFIER && buf->id2ast && buf->id2ast ->type == Yosys::AST::AST_TYPEDEF) {
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- // If the identifier points to a typedef, use the type that is stored inside the typedef (children[0]).
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- log_assert (buf->id2ast ->children .size ());
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- buf->id2ast = buf->id2ast ->children [0 ];
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- }
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- buf-> detectSignWidth ( width_hint, sign_hint);
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+ // if (buf->type == Yosys::AST::AST_IDENTIFIER && buf->id2ast && buf->id2ast->type == Yosys::AST::AST_TYPEDEF) {
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+ // // If the identifier points to a typedef, use the type that is stored inside the typedef (children[0]).
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+ // log_assert(buf->id2ast->children.size());
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+ // buf->id2ast = buf->id2ast->children[0];
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+ // }
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+ detect_sign_width_proxy (buf, width_hint, sign_hint);
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if (buf->type == Yosys::AST::AST_IDENTIFIER) {
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id_ast = buf->id2ast ;
@@ -3285,7 +3294,7 @@ skip_dynamic_range_lvalue_expansion:;
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RTLIL::unescape_id (ast_node->str ).c_str ());
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int child_width_hint = width_hint;
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bool child_sign_hint = sign_hint;
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- ast_node->children [0 ]-> detectSignWidth ( child_width_hint, child_sign_hint);
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+ detect_sign_width_proxy ( ast_node->children [0 ], child_width_hint, child_sign_hint);
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x = ast_node->children [0 ]->asReal (child_sign_hint);
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}
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@@ -3296,7 +3305,7 @@ skip_dynamic_range_lvalue_expansion:;
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RTLIL::unescape_id (ast_node->str ).c_str ());
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int child_width_hint = width_hint;
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bool child_sign_hint = sign_hint;
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- ast_node->children [1 ]-> detectSignWidth ( child_width_hint, child_sign_hint);
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+ detect_sign_width_proxy ( ast_node->children [1 ], child_width_hint, child_sign_hint);
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y = ast_node->children [1 ]->asReal (child_sign_hint);
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}
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@@ -3364,7 +3373,7 @@ skip_dynamic_range_lvalue_expansion:;
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int exp_width = -1 ;
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bool exp_sign = false ;
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Yosys::AST::AstNode *exp = ast_node->children [0 ];
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- exp-> detectSignWidth ( exp_width, exp_sign, NULL );
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+ detect_sign_width_proxy (exp, exp_width, exp_sign, NULL );
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newNode = ast_node->mkconst_int (0 , false );
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@@ -3997,10 +4006,10 @@ replace_fcall_later:;
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if (choice->type == Yosys::AST::AST_CONSTANT) {
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int other_width_hint = width_hint;
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bool other_sign_hint = sign_hint, other_real = false ;
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- not_choice-> detectSignWidth ( other_width_hint, other_sign_hint, &other_real);
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+ detect_sign_width_proxy (not_choice, other_width_hint, other_sign_hint, &other_real);
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if (other_real) {
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newNode = new Yosys::AST::AstNode (Yosys::AST::AST_REALVALUE);
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- choice-> detectSignWidth ( width_hint, sign_hint);
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+ detect_sign_width_proxy (choice, width_hint, sign_hint);
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newNode->realvalue = choice->asReal (sign_hint);
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} else {
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RTLIL::Const y = choice->bitsAsConst (width_hint, sign_hint);
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