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Change Signal.fromList's tail from errorX to error
By making the undefined tail of a signal created with fromList into an error instead of errorX, this makes it clear when you're trying use a signal without enough input data. A problem with the errorX was that in certain circumstances it can be turned into a signal full of XException. That can turn into a signal full of undefined BitVectors. And when that is used as the basis for the expected values of a outputVerifierBitVector you end up with a testbench that reports everything is fine for some (possibly big) part of the test. Also add HasCallStack to Signal.fromList to help with tracing this error.
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clash-prelude/src/Clash/Explicit/Prelude.hs

+1-1
Original file line numberDiff line numberDiff line change
@@ -263,7 +263,7 @@ window clk rst en x = res
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-- @
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--
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-- >>> simulateB (windowD3 systemClockGen resetGen enableGen) [1::Int,1,2,3,4] :: [Vec 3 Int]
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-- [0 :> 0 :> 0 :> Nil,0 :> 0 :> 0 :> Nil,1 :> 0 :> 0 :> Nil,2 :> 1 :> 0 :> Nil,3 :> 2 :> 1 :> Nil,4 :> 3 :> 2 :> Nil,...
266+
-- [0 :> 0 :> 0 :> Nil,0 :> 0 :> 0 :> Nil,1 :> 0 :> 0 :> Nil,2 :> 1 :> 0 :> Nil,3 :> 2 :> 1 :> Nil,4 :> 3 :> 2 :> Nil...
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-- ...
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windowD
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:: ( KnownNat n

clash-prelude/src/Clash/Prelude.hs

+2-2
Original file line numberDiff line numberDiff line change
@@ -244,7 +244,7 @@ functions a type class called 'Clash.Class.Parity.Parity' is available at
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-- > window4 = window
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--
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-- >>> simulateB @System window4 [1::Int,2,3,4,5] :: [Vec 4 Int]
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-- [1 :> 0 :> 0 :> 0 :> Nil,2 :> 1 :> 0 :> 0 :> Nil,3 :> 2 :> 1 :> 0 :> Nil,4 :> 3 :> 2 :> 1 :> Nil,5 :> 4 :> 3 :> 2 :> Nil,...
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-- [1 :> 0 :> 0 :> 0 :> Nil,2 :> 1 :> 0 :> 0 :> Nil,3 :> 2 :> 1 :> 0 :> Nil,4 :> 3 :> 2 :> 1 :> Nil,5 :> 4 :> 3 :> 2 :> Nil...
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-- ...
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window
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:: ( HiddenClockResetEnable dom
@@ -267,7 +267,7 @@ window = hideClockResetEnable E.window
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-- > windowD3 = windowD
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--
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-- >>> simulateB @System windowD3 [1::Int,2,3,4] :: [Vec 3 Int]
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-- [0 :> 0 :> 0 :> Nil,1 :> 0 :> 0 :> Nil,2 :> 1 :> 0 :> Nil,3 :> 2 :> 1 :> Nil,4 :> 3 :> 2 :> Nil,...
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-- [0 :> 0 :> 0 :> Nil,1 :> 0 :> 0 :> Nil,2 :> 1 :> 0 :> Nil,3 :> 2 :> 1 :> Nil,4 :> 3 :> 2 :> Nil...
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-- ...
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windowD
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:: ( HiddenClockResetEnable dom

clash-prelude/src/Clash/Prelude/Moore.hs

+1-1
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ let macT s (x,y) = x * y + s
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-- @
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--
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-- >>> simulate @System mac [(0,0),(1,1),(2,2),(3,3),(4,4)]
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-- [0,0,1,5,14,30,...
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-- [0,0,1,5,14,30...
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-- ...
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--
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-- Synchronous sequential functions can be composed just like their

clash-prelude/src/Clash/Signal/Internal.hs

+4-4
Original file line numberDiff line numberDiff line change
@@ -204,7 +204,7 @@ import Clash.NamedTypes
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import Clash.Promoted.Nat (SNat (..), snatToNum, snatToNatural)
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import Clash.Promoted.Symbol (SSymbol (..), ssymbolToString)
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import Clash.XException
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(NFDataX(..), errorX, isX, deepseqX, defaultSeqX, seqX)
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(NFDataX(..), isX, deepseqX, defaultSeqX, seqX)
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{- $setup
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>>> :set -XDataKinds
@@ -1689,8 +1689,8 @@ sampleN n = take n . sample
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-- [1,2]
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--
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-- __NB__: This function is not synthesizable
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fromList :: NFDataX a => [a] -> Signal dom a
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fromList = Prelude.foldr (\a b -> deepseqX a (a :- b)) (errorX "finite list")
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fromList :: (HasCallStack,NFDataX a) => [a] -> Signal dom a
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fromList = Prelude.foldr (\a b -> deepseqX a (a :- b)) (error "finite list")
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-- * Simulation functions (not synthesizable)
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@@ -1748,7 +1748,7 @@ sampleN_lazy n = take n . sample_lazy
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-- [1,2]
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--
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-- __NB__: This function is not synthesizable
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fromList_lazy :: [a] -> Signal dom a
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fromList_lazy :: HasCallStack => [a] -> Signal dom a
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fromList_lazy = Prelude.foldr (:-) (error "finite list")
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-- * Simulation functions (not synthesizable)

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