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Move i2c to clash cores #2584

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c35889b
Move I2C example files to `clash-cores`
lmbollen Oct 3, 2023
9616fb2
Fix warnings in `i2c` core.
lmbollen Oct 3, 2023
14af81e
Add comments to i2c core
lmbollen Oct 10, 2023
c4bb357
Make I2C core polymorphic in its domain
lmbollen Oct 11, 2023
7bf0b2f
Remove HDL build test for I2C in examples
lmbollen Oct 18, 2023
5e0368e
Refactor i2c core to be more user friendly
lmbollen Oct 26, 2023
a1ce13e
Add I2C unit test to `clash-cores:unittests`
lmbollen Oct 31, 2023
c13627b
Respect boolean values of acknowledgements. Make acknowledgements com…
hiddemoll Jan 24, 2024
98e806c
Fix incorrect I2C test
hiddemoll Apr 9, 2024
28fdb7a
Refactor I2C core and unittest
hiddemoll Apr 9, 2024
0d2cbb7
Add debug flag to I2C unittest
hiddemoll Apr 9, 2024
ca4a097
Add module headers to all moved I2C modules
hiddemoll Apr 10, 2024
7676ced
Extend haddock documentation for I2C core
hiddemoll Apr 10, 2024
59cb3c7
Move I2C core to Experimental submodule
hiddemoll Apr 10, 2024
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31 changes: 0 additions & 31 deletions clash-cores/src/Clash/Cores/I2C.hs
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Original file line number Diff line number Diff line change
Expand Up @@ -7,37 +7,6 @@ import Clash.Prelude hiding (read)
import Clash.Cores.I2C.BitMaster
import Clash.Cores.I2C.ByteMaster

{-# ANN i2c
(Synthesize
{ t_name = "i2c"
, t_inputs = [ PortName "clk"
, PortName "arst"
, PortName "rst"
, PortName "ena"
, PortName "clkCnt"
, PortName "start"
, PortName "stop"
, PortName "read"
, PortName "write"
, PortName "ackIn"
, PortName "din"
, PortProduct "i2c"
[ PortName "sda"
, PortName "sdaEn"]
]
, t_output = PortProduct ""
[ PortName "dout"
, PortName "hostAck"
, PortName "busy"
, PortName "al"
, PortName "ackOut"
, PortProduct "i2cO"
[ PortName "scl"
, PortName "sclOEn"
, PortName "sda"
, PortName "sdaOEn"
]]
}) #-}
-- | Core for I2C communication
i2c ::
forall dom .
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29 changes: 1 addition & 28 deletions clash-cores/src/Clash/Cores/I2C/BitMaster.hs
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Expand Up @@ -52,34 +52,7 @@ type BitMasterI = (Bool,Bool,Unsigned 16,BitCtrlSig,I2CIn)
-- 3. Contains the SCL and SDA output signals
type BitMasterO = (BitRespSig,Bool,I2COut)

{-# ANN bitMaster
(Synthesize
{ t_name = "bitmaster"
, t_inputs = [ PortName "clk"
, PortName "arst"
, PortName "gen"
, PortProduct ""
[ PortName "rst"
, PortName "ena"
, PortName "clkCnt"
, PortProduct ""
[ PortName "cmd"
, PortName "din" ]
, PortName "i2cI" ]
]
, t_output = PortProduct ""
[ PortProduct ""
[ PortName "cmdAck"
, PortName "al"
, PortName "dout" ]
, PortName "busy"
, PortProduct "i2c"
[ PortName "sda"
, PortName "sdaEn"
, PortName "scl"
, PortName "sclEn" ]
]
}) #-}

bitMaster
:: KnownDomain dom
=> Clock dom
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23 changes: 0 additions & 23 deletions clash-cores/src/Clash/Cores/I2C/ByteMaster.hs
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Expand Up @@ -48,29 +48,6 @@ type ByteMasterI = (Bool,Bool,Bool,Bool,Bool,Bool,BitVector 8,BitRespSig)
-- 4 Bitmaster control signals
type ByteMasterO = (Bool,Bool,BitVector 8,BitCtrlSig)

{-# ANN byteMaster
(Synthesize
{ t_name = "bytemaster"
, t_inputs = [ PortName "clk"
, PortName "arst"
, PortName "gen"
, PortProduct ""
[ PortName "rst"
, PortName "start"
, PortName "stop"
, PortName "read"
, PortName "write"
, PortName "ackIn"
, PortName "din"
, PortName "bitResp" ]
]
, t_output = PortProduct ""
[ PortName "hostAck"
, PortName "ackOut"
, PortName "dout"
, PortName "bitCtrl"
]
}) #-}
-- | Byte level controller, takes care of correctly executing i2c communication
-- based on the supplied control signals. It should be instantiated alongside 'bitMaster'.
-- The outgoing bitCtrl' controls the 'bitMaster' whose 'bitResp' should be supplied
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2 changes: 1 addition & 1 deletion clash-cores/test/Test/Cores/I2C.hs
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Expand Up @@ -31,7 +31,7 @@ system0 clk arst = bundle (registerFile,done,fault)
-- See: https://github.com/clash-lang/clash-compiler/pull/2511
{-# CLASH_OPAQUE system0 #-}

{-# ANN system Synthesize { t_name = "system", t_inputs = [], t_output = PortName "" } #-}
{-# ANN system (defSyn "system") #-}
system :: Signal System (Vec 16 (Unsigned 8), Bool, Bool)
system = system0 systemClockGen resetGen

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18 changes: 0 additions & 18 deletions tests/Main.hs
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Expand Up @@ -158,24 +158,6 @@ runClashTest = defaultMain $ clashTestRoot
, clashTestGroup "crc32"
[ runTest "CRC32" def
]
, clashTestGroup "i2c"
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The I2C test is:

  1. The only test in the clash testsuite that has multiple synthesize annotations
  2. Tests SimIO in a common user scenario.

So I would like it if this test wasn't removed. And given that the I2C core in clash cores has a new API, perhaps we can either just:

  1. Keep the old domain-monomorphic code in the examples directory
  2. Or move the old domain-monomorphic code to a test directory
    So that we still have a test with multiple Synthesize annotations.

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  1. Sounds like the best option to me!

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Also agree with 2, we can just put the old code in a test directory.

[ let _opts = def { clashFlags=["-O2","-fclash-component-prefix","test"]
, buildTargets=BuildSpecific ["test_i2c"]
, hdlSim=[]
}
in runTest "I2C" _opts
,
-- TODO: this uses finish_and_return, with is Icarus Verilog only.
-- see: https://github.com/clash-lang/clash-compiler/issues/2265
let _opts = def { buildTargets = BuildSpecific ["system"]
, hdlTargets = [Verilog]
, hdlLoad = [IVerilog]
, hdlSim = [IVerilog]
, vvpStdoutNonEmptyFail = False
}
in runTest "I2Ctest" _opts

]
]
, clashTestGroup "tests"
[ clashTestGroup "shouldfail"
Expand Down