coprocessor generator

.github/workflows/ci.yml

@@ -61,7 +61,8 @@ jobs:
             cmake \
             graphviz \
             bc \
-            ghdl
+            ghdl \
+            verilator
 
       - name:
         run: |

openasip/data/ProGe/cvxif_coprocessor.sv.tmpl

@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2025 Tampere University.
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+module FUNAME_coprocessor
+  import cvxif_sup_pkg::*;
+#(
+    // CVXIF Types According to the CVA6
+    parameter  int unsigned NrRgprPorts         = 3,
+    parameter  type         readregflags_t      = logic,
+    parameter  type         writeregflags_t     = logic,
+    parameter  type         id_t                = logic,
+    parameter  type         hartid_t            = logic,
+    parameter  type         x_compressed_req_t  = logic,
+    parameter  type         x_compressed_resp_t = logic,
+    parameter  type         x_issue_req_t       = logic,
+    parameter  type         x_issue_resp_t      = logic,
+    parameter  type         x_register_t        = logic,
+    parameter  type         x_commit_t          = logic,
+    parameter  type         x_result_t          = logic,
+    parameter  type         cvxif_req_t         = logic,
+    parameter  type         cvxif_resp_t        = logic,
+    localparam type         registers_t         = logic [NrRgprPorts-1:0][31:0]
+) (
+    input  logic        clk_i,        // Clock
+    input  logic        rst_ni,       // Asynchronous reset active low
+    input  cvxif_req_t  cvxif_req_i,
+    output cvxif_resp_t cvxif_resp_o
+); 
+
+  //Compressed interface
+  logic               x_compressed_valid_i;
+  logic               x_compressed_ready_o;
+  x_compressed_req_t  x_compressed_req_i;
+  x_compressed_resp_t x_compressed_resp_o;
+  //Issue interface
+  logic               x_issue_valid_i;
+  logic               x_issue_ready_o;
+  x_issue_req_t       x_issue_req_i;
+  x_issue_resp_t      x_issue_resp_o;
+  //Commit interface
+  logic               x_commit_valid_i;
+  x_commit_t          x_commit_i;
+  // Register interface signals
+  x_register_t        register;
+  logic               register_valid;
+  //Result interface
+  logic               x_result_valid_o;
+  logic               x_result_ready_i;
+  x_result_t          x_result_o;
+
+  assign x_compressed_valid_i            = cvxif_req_i.compressed_valid;
+  assign x_compressed_req_i              = cvxif_req_i.compressed_req;
+  assign x_issue_valid_i                 = cvxif_req_i.issue_valid;
+  assign x_issue_req_i                   = cvxif_req_i.issue_req;
+  assign x_commit_valid_i                = cvxif_req_i.commit_valid;
+  assign x_commit_i                      = cvxif_req_i.commit;
+  assign x_result_ready_i                = cvxif_req_i.result_ready;
+  assign register                        = cvxif_req_i.register;
+  assign register_valid                  = cvxif_req_i.register_valid;
+
+  assign cvxif_resp_o.compressed_ready = x_compressed_ready_o;
+  assign cvxif_resp_o.compressed_resp  = x_compressed_resp_o;
+  assign cvxif_resp_o.issue_ready      = x_issue_ready_o;
+  assign cvxif_resp_o.issue_resp       = x_issue_resp_o;
+  assign cvxif_resp_o.result_valid     = x_result_valid_o;
+  assign cvxif_resp_o.result           = x_result_o;
+  assign cvxif_resp_o.register_ready   = x_issue_ready_o;
+
+  //Compressed interface handler/decoder
+  cvxifcompressed_decoder #(
+    .x_compressed_req_t (x_compressed_req_t),
+    .x_compressed_resp_t(x_compressed_resp_t)
+  ) compressed_decoder_i (
+    .clk_i              (clk_i), //No current use
+    .compressed_valid   (x_compressed_valid_i),
+    .x_compressed_req   (x_compressed_req_i),
+    .x_compressed_resp  (x_compressed_resp_o),
+    .compressed_ready   (x_compressed_ready_o)
+  );
+
+  logic[cvxif_sup_pkg::NConfigbits_C-1 : 0]       configbits_in_i;  // For input config bits
+  logic               				    	              x_result_valid_i; // For intermediate result valid			
+  logic[cvxif_sup_pkg::NConfigbits_C-1 : 0]       configbits_o;     // For config bits out the FU
+  logic[cvxif_sup_pkg::X_RFW_WIDTH-1 : 0]         result_data_out;  // For data out from the function unit
+  logic instr_accept, instr_ready;
+  logic[31:0] instruction_in;
+  CONFIG_DEFINE
+  assign x_issue_ready_o       = instr_ready && register.rs_valid[0] && register.rs_valid[1] && (NrRgprPorts == 3 ? register.rs_valid[2] : 1'b1);
+  assign x_issue_resp_o.accept = instr_accept;
+  assign instruction_in        = cvxif_sup_pkg::OpcodeMask & x_issue_req_i.instr;
+  assign x_result_valid_i      = x_issue_valid_i & x_issue_ready_o & instr_accept;
+  assign configbits_in_i       = {x_result_valid_i, x_issue_req_i.instr[11:7], x_issue_resp_o.writeback, x_issue_req_i.hartid, x_issue_req_i.id};
+
+  fu_FUNAME function_unit_i (
+      .clk(clk_i),
+      .rstx(rst_ni),
+      .operation_enable_in(x_issue_valid_i),
+      .result_ready_in(x_result_ready_i),
+      .configbits_in(configbits_in_i),
+      .operation_in(instruction_in), 
+      CONFIG_ENINPUT1.data_OUTPUTF_out(result_data_out),
+      CONFIG_BITS.configbits_out(configbits_o),
+      .accept_o(instr_accept),
+      .ready_o(instr_ready)
+  );
+
+  always_comb begin
+    x_issue_resp_o.writeback = 1'b0;
+    if (instr_accept) begin
+        x_issue_resp_o.writeback = 1'b1;
+    end
+  end
+
+  instr_tracker_FUNAME #(
+    .IdWidth(cvxif_sup_pkg::X_ID_WIDTH),
+    .HWidth(cvxif_sup_pkg::X_HARTID_WIDTH),
+    .IdBits(cvxif_sup_pkg::IdBits)
+  ) instruction_tracker_i (
+    .clk(clk_i),
+    .rstx(rst_ni),
+    .commit_hartid_i(x_commit_i.hartid),      
+    .commit_id_i(x_commit_i.id),
+    .commit_kill_i(x_commit_i.commit_kill),
+    .commit_valid_i(x_commit_valid_i),
+    .issue_hartid_i(x_issue_req_i.hartid),
+    .issue_id_i(x_issue_req_i.id),
+    .issue_valid_i(x_issue_resp_o.accept),
+    SEARCH_CONFIGOUT_COMMIT_TRACKER.output_hartid_i(configbits_o[cvxif_sup_pkg::X_ID_WIDTH + cvxif_sup_pkg::X_HARTID_WIDTH - 1 : cvxif_sup_pkg::X_ID_WIDTH]),
+    .output_id_i(configbits_o[cvxif_sup_pkg::X_ID_WIDTH - 1 : 0]),
+    .output_valid_i(configbits_o[cvxif_sup_pkg::NConfigbits_C-1])
+  );
+
+  always_comb begin
+    x_result_valid_o   = configbits_o[cvxif_sup_pkg::NConfigbits_C-1];  
+    x_result_o.id      = configbits_o[cvxif_sup_pkg::X_ID_WIDTH - 1 : 0]; 
+    x_result_o.rd      = configbits_o[cvxif_sup_pkg::NConfigbits_C-2 : cvxif_sup_pkg::NConfigbits_C - 1 - 5];                             
+    x_result_o.we      = configbits_o[cvxif_sup_pkg::X_ID_WIDTH + cvxif_sup_pkg::X_HARTID_WIDTH + cvxif_sup_pkg::X_DUALWRITE : cvxif_sup_pkg::X_ID_WIDTH + cvxif_sup_pkg::X_HARTID_WIDTH] & x_result_valid_o;              
+    x_result_o.hartid  = configbits_o[cvxif_sup_pkg::X_ID_WIDTH + cvxif_sup_pkg::X_HARTID_WIDTH - 1 : cvxif_sup_pkg::X_ID_WIDTH];
+    x_result_o.data    = result_data_out;
+  end
+
+endmodule

openasip/data/ProGe/cvxifcompressed_decoder.sv.tmpl

@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2025 Tampere University.
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+//Module for the compressed interface handling
+
+module cvxifcompressed_decoder
+#(
+    parameter type                    x_compressed_req_t           = logic,
+    parameter type                    x_compressed_resp_t          = logic
+) (
+    input  logic               clk_i, //Might not need a clock since the response should be given on the same cycle as the input.
+    input  logic               compressed_valid,
+    input  x_compressed_req_t  x_compressed_req,
+    output x_compressed_resp_t x_compressed_resp,
+    output logic               compressed_ready
+);
+  //TODO Check the received compressed one is identifiable(x_compressed_req_t.instr) by checking through the compressed instr package
+  //Output the relevant 32bit version on x_compressed_resp_t.instr and make x_compressed_resp_t.accept while compressed_ready asserted.
+  //CPU can change all the values until the compressed_ready=1(CPU can retract as well, so the compressed decode task should be combinational)
+  //Currently rejects all the incoming compressed requests.
+
+  always_comb begin 
+    if (compressed_valid) begin
+      x_compressed_resp.accept  = '0;
+      compressed_ready            = '1;
+    end
+    else begin
+      x_compressed_resp.accept  = '0;
+      compressed_ready            = '0;
+    end
+  end
+
+endmodule
+
+

openasip/data/ProGe/rocc_copro.sv.tmpl

@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2025 Tampere University.
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+module FUNAME_coprocessor
+ #( parameter xLen = 64,
+     PRV_SZ = 2
+ )
+ ( input clock,
+    input                                reset,
+    output                               cmd_ready,
+    input                                cmd_valid,
+    input [6:0]                          cmd_bits_inst_funct,
+    input [4:0]                          cmd_bits_inst_rs2,
+    input [4:0]                          cmd_bits_inst_rs1,
+    input                                cmd_bits_inst_xd,
+    input                                cmd_bits_inst_xs1,
+    input                                cmd_bits_inst_xs2,
+    input [4:0]                          cmd_bits_inst_rd,
+    input [6:0]                          cmd_bits_inst_opcode,
+    input [xLen-1:0]                     cmd_bits_rs1,
+    input [xLen-1:0]                     cmd_bits_rs2,
+    input                                cmd_bits_status_debug,
+    input                                cmd_bits_status_cease,
+    input                                cmd_bits_status_wfi,
+    input [63:0]                         cmd_bits_status_isa,
+    input [PRV_SZ-1:0]                   cmd_bits_status_dprv,
+    input                                cmd_bits_status_dv,
+    input [PRV_SZ-1:0]                   cmd_bits_status_prv,
+    input                                cmd_bits_status_v,
+    input                                cmd_bits_status_sd,
+    input [22:0]                         cmd_bits_status_zero2,
+    input                                cmd_bits_status_mpv,
+    input                                cmd_bits_status_gva,
+    input                                cmd_bits_status_mbe,
+    input                                cmd_bits_status_sbe,
+    input [1:0]                          cmd_bits_status_sxl,
+    input [1:0]                          cmd_bits_status_uxl,
+    input                                cmd_bits_status_sd_rv32,
+    input [7:0]                          cmd_bits_status_zero1,
+    input                                cmd_bits_status_tsr,
+    input                                cmd_bits_status_tw,
+    input                                cmd_bits_status_tvm,
+    input                                cmd_bits_status_mxr,
+    input                                cmd_bits_status_sum,
+    input                                cmd_bits_status_mprv,
+    input [1:0]                          cmd_bits_status_xs,
+    input [1:0]                          cmd_bits_status_fs,
+    input [1:0]                          cmd_bits_status_vs,
+    input [1:0]                          cmd_bits_status_mpp,
+    input [0:0]                          cmd_bits_status_spp,
+    input                                cmd_bits_status_mpie,
+    input                                cmd_bits_status_ube,
+    input                                cmd_bits_status_spie,
+    input                                cmd_bits_status_upie,
+    input                                cmd_bits_status_mie,
+    input                                cmd_bits_status_hie,
+    input                                cmd_bits_status_sie,
+    input                                cmd_bits_status_uie,
+    input                                resp_ready,
+    output                               resp_valid,
+    output [4:0]                         resp_bits_rd,
+    output [xLen-1:0]                    resp_bits_data,
+    output                               busy
+ );
+
+  localparam [4:0] bits_reg = 5'b00000;
+
+  logic [63:0] inter_rs1;
+  logic [63:0] inter_rs2;
+  logic [6:0]  inter_opcode;
+  logic [6:0]  inter_func;
+  logic [4:0]  inter_rd;
+
+  reg [63:0] inter_rs1_r;
+  reg [63:0] inter_rs2_r;
+  reg [31:0]  inter_opcode_r;
+  reg [6:0]  inter_func_r;
+  reg [4:0]  inter_rd_r;
+  reg inter_en_r;
+  reg inter_cmd_valid;
+
+  assign busy = '0; // Expects the core always accepts the data from the coprocessor
+  assign cmd_ready = '1;
+  assign inter_rs1 = cmd_bits_rs1;
+  assign inter_rs2 = cmd_bits_rs2;
+  assign inter_opcode = cmd_bits_inst_opcode;
+  assign inter_func = cmd_bits_inst_funct;
+  assign inter_rd = cmd_bits_inst_rd;
+  assign inter_cmd_valid = cmd_valid;
+
+  // CMD Control COMB
+  always_comb begin
+    inter_rs1_r     = '0;
+    inter_rs2_r     = '0;
+    inter_opcode_r  = '0;
+    inter_rd_r      = '0;
+    inter_en_r      = '0;
+      if (inter_cmd_valid == 1) begin   // Valid from the ROCC
+          inter_rs1_r     = inter_rs1;
+          inter_rs2_r     = inter_rs2;
+          inter_opcode_r  = {inter_func, bits_reg, bits_reg, cmd_bits_inst_xd, cmd_bits_inst_xs1, cmd_bits_inst_xs2, bits_reg, inter_opcode};
+          inter_rd_r      = inter_rd;
+          inter_en_r      = '1;
+      end 
+  end
+
+ // FU
+ fu_FUNAME fu_functionunit_i (
+      .clk(clock),
+      .rstx(~reset),
+      .glock_in(0),
+      .operation_in(inter_opcode_r),
+      .data_P1_in(inter_rs1_r[31:0]),
+      .operation_enable_in(inter_en_r),
+      .data_P2_in(inter_rs2_r[31:0]),
+      .configs_in({inter_rd_r,inter_en_r}),
+      .configs_out(resp_bits_rd),
+      .out_ready(resp_ready),
+      .out_valid(resp_valid),
+      .data_P3_out(resp_bits_data[31:0])
+  );
+
+endmodule

openasip/scheduler/testbench/scheduler_tester.py

@@ -1238,7 +1238,7 @@ def printLatexHeader(self, firstColumnWidth=30, valueColumnWidth=16):
         for i in range(0, len(moreStats)*len(self.archs)):
             cols += 'l|'
 
-        sys.stdout.write('\\begin{tabular}{|l|%s} \hline\n' % cols)
+        sys.stdout.write('\\begin{tabular}{|l|%s} \\hline\n' % cols)
         sys.stdout.write(''.ljust(firstColumnWidth))
         sys.stdout.write(' & ')
         archsPrinted = 0
@@ -1272,14 +1272,14 @@ def printLatexHeader(self, firstColumnWidth=30, valueColumnWidth=16):
                 if archsPrinted < len(self.archs):
                     sys.stdout.write(' &')
 
-        sys.stdout.write('\\\\ \hline\n')
+        sys.stdout.write('\\\\ \\hline\n')
 
     def printLatexRow(self, testCase, firstColumnWidth=30):
         """
         Prints a single row of the LaTeX table.
         """
         global moreStats
-        sys.stdout.write(os.path.basename(testCase.directory).replace('_', '\_').ljust(firstColumnWidth))
+        sys.stdout.write(os.path.basename(testCase.directory).replace('_', '\\_').ljust(firstColumnWidth))
         sys.stdout.write(' & ')
 
         archsPrinted = 0