Tired of clicking around in Xilinx ISE? Run your builds from the command line!
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Xilinx ISE, ideally 14.7 (the final version)
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GNU (or compatible?) Make
Install this through Cygwin on Windows.
To start building a project, you will need to create a file project.cfg in
the top level of your project. This file is a text file sourced by Make, so
it consists of KEY = value pairs. It must define at least the following keys:
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PROJECTThe name of the project, used as a name for certain intermediate files, and as the default name for the top-level module and constraints file.
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TARGET_PARTThe full part-speed-package identifier for the Xilinx part to be targeted, e.g.
xc6slx9-2-tqg144. -
XILINXThe path to the appropriate binaries directory of the target Xilinx ISE install, e.g.
/cygdrive/c/Xilinx/14.7/ISE_DS/ISEor/opt/Xilinx/14.7/ISE_DS/ISEfor typical installs. -
VSOURCEand/orVHDSOURCEThe space-separated names of all Verilog and/or VHDL source files to be used in the project.
You can define these on multiple lines using
+=, e.g.VSOURCE += foo.v VSOURCE += bar.v
A simple project.cfg may thus resemble:
PROJECT = example
TARGET_PART = xc6slx9-2-cpg196
XILINX = /cygdrive/c/Xilinx/14.7/ISE_DS/ISE/bin/nt64
VSOURCE = example.v
A number of other keys can be set in the project configuration, including:
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XILINX_PLATFORMThe Xilinx name for the platform to build for, e.g.
nt64orlin.nt64is used by default for Windows systems, andlin64for Linux systems, so you only need to set this if you explicitly need to use the 32-bit version of the tools for some reason. -
TOPLEVELThe name of the top-level module to be used in the project. (Defaults to
$PROJECT.) -
CONSTRAINTSThe name of the constraints file (
.ucf) to be used for the project. (Defaults to$PROJECT.ucf.) -
COMMON_OPTSExtra command-line options to be passed to all ISE executables. Defaults to
-intstyle xflow. -
XST_OPTS,NGDBUILD_OPTS,MAP_OPTS,PAR_OPTS,BITGEN_OPTS,TRACE_OPTS,FUSE_OPTSExtra command-line options to be passed to the corresponding ISE tools. All default to empty.
Note that
XST_OPTSwill not appear on the command line during compilation, as the XST options are embedded in a script file.MAP_OPTSandPAR_OPTScan be set to-mt 2to use multithreading, which may speed up compilation of large designs.BITGEN_OPTScan be set to-g Compressto apply bitstream compression. -
PROGRAMMERThe name of the programmer to be used for
make prog. Currently supported values are:-
impactUses Xilinx iMPACT for programming, using a batch file named
impact.cmdby default. The iMPACT command line may be overridden by settingIMPACT_OPTS.A typical batch file may resemble:
setMode -bscan setCable -p auto addDevice -p 1 -file build/projectname.bit program -p 1 quit -
digilentUses the Digilent JTAG utility for programming, which must be installed separately. The name of the board must be set as
DJTG_DEVICE; the path to the djtgcfg executable can be set asDJTG_EXE, and the index of the device can be set asDJTG_INDEX. -
xc3sprogUses the xc3sprog utility for programming, which must also be installed separately. The cable name must be set as
XC3SPROG_CABLE; additional options can be set asXC3SPROG_OPTS.
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The Xilinx ISE Makefile implements the following targets:
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make default(or justmake)Builds the bitstream.
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make cleanRemoves the build directory.
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make progWrites the bitstream to a target device. Requires some additional configuration; see below for details.
is a work in progress.
The following features are not currently implemented. (Pull requests are encouraged!)
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Generation of SPI or other unusual programming files
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CPLD synthesis
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Synthesis tools other than XST
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Display and/or handling of warnings and errors from
build/_xmsgs -
Anything else (open an issue?)
To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any warranty.
See LICENSE.md for details.