@@ -169,9 +169,26 @@ namespace hal
169169
170170 if ( clk->get_num_of_sources () > 1 )
171171 {
172- log_error ( " clock_tree_extractor" ,
173- " invalid number of sources for clock net with ID " + std::to_string ( clk->get_id () ) );
174- continue ;
172+ bool valid = true ;
173+ for ( const Endpoint *source_ep : clk->get_sources () )
174+ {
175+ const Gate *gate = source_ep->get_gate ();
176+ if ( !( is_buffer (gate) || is_inverter (gate) ) )
177+ {
178+ // In theory, it should be either all buffers or all inverters. But depending on
179+ // extraction results, e.g., it could happen that a buffer is split into two inverters.
180+ // So I just assume it is fine if all the sources are either a buffer or an inverter
181+ // without enforcing strict buffer only or inverter only.
182+ valid = false ;
183+ break ;
184+ }
185+ }
186+ if ( !valid )
187+ {
188+ log_error ( " clock_tree_extractor" ,
189+ " invalid number of sources for clock net with ID " + std::to_string ( clk->get_id () ) );
190+ continue ;
191+ }
175192 }
176193 else if ( clk->is_global_input_net () )
177194 {
@@ -187,7 +204,11 @@ namespace hal
187204 continue ;
188205 }
189206
190- queue.push ( { ff, clk->get_sources ().front ()->get_gate (), std::vector<const Gate *>{ ff } } );
207+ for ( const Endpoint *source_ep : clk->get_sources () )
208+ {
209+ const Gate *gate = source_ep->get_gate ();
210+ queue.push ( { ff, gate, std::vector<const Gate *>{ ff } } );
211+ }
191212
192213 vertices.insert ( (void *) ff );
193214 ptrs_to_type[(void *) ff] = PtrType::GATE;
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