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178 Open 276 Closed
178 Open 276 Closed
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Issues list

Average pooling result_t bug
#1297 opened May 12, 2025 by jmitrevs
Weight Pruning on FPGA bug
#1295 opened May 10, 2025 by Smitashree-code
3
Exception: ERROR: Unsupported layer type: BayesianDropout bug
#1293 opened May 8, 2025 by shiyishiguang
1
SeLU activation range? bug
#1287 opened May 1, 2025 by jmitrevs
1
Vivado_hls 2019.2 synthesis error bug
#1283 opened Apr 29, 2025 by Smitashree-code
5
error in config bug
#1280 opened Apr 28, 2025 by Gabriel-MarcoSilva
1
Packaging files setup.cfg and setup.py have been removed bug question
#1271 opened Apr 12, 2025 by GiuseppeDiGuglielmo
@JanFSchulte @vloncar
3
g++ error when running build bug
#1269 opened Apr 11, 2025 by ixiotidi
4 tasks
5
hls4ml fpga_backend fails when using a Resize node with no ROI using #1266 fix (Brevitas -> QONNX) bug
#1268 opened Apr 11, 2025 by The-Padi
4 tasks done
1
hls4ml config_from_onnx_model fails when using a Resize node with no ROI (Brevitas -> QONNX) bug
#1266 opened Apr 10, 2025 by Dyoxyz
4 tasks done
3
Unsupported aggregate pragma/directive on variable 'layer63_out' as the bit-width after aggregation (6272) is larger than 4096 bug
#1245 opened Mar 26, 2025 by layson-inventor
4 tasks
1
TLAST Signal Missing in IP Core Generated by HLS4ML bug
#1244 opened Mar 25, 2025 by SIRIDHARI
report not found bug
#1231 opened Mar 15, 2025 by howard-liang-B
5
Non-optimal II optimization for Pointwise Conv1D bug enhancement
#1223 opened Mar 11, 2025 by Duchstf
1
Softmax max exp_table lookup may include the sign bit
#1221 opened Mar 9, 2025 by calad0i
Vivado HLS Export IP Fails: [BD 5-390] IP definition not found for VLNV: xilinx.com:hls:myproject_axi:1.0 bug
#1216 opened Mar 5, 2025 by alvarorramos
4
Failures in test_sr.py bug
#1207 opened Feb 21, 2025 by jmitrevs
4 tasks done
@vloncar
8
Exception: ERROR: Unsupported operation type: QuantizeLinear bug
#1197 opened Feb 17, 2025 by howard-liang-B
7
Catapult with io_stream: Using Channel 'layer3_out' as both input and output is unsupported. (HIER-11) bug
#1180 opened Jan 31, 2025 by sei-jgwohlbier
4 tasks done
4
Pre-synthesis failed in both project and in part7a_bitstream tutorial bug
#1157 opened Dec 19, 2024 by sdubey11
4 tasks done
4
TF model implementation in tf version 2.18.0 bug
#1150 opened Dec 13, 2024 by ixiotidi
4 tasks
2
PyTorch: fails on model with multiple return values. bug
#1147 opened Dec 12, 2024 by sei-jgwohlbier
4 tasks done
1
Error on config_from_keras_model: [IndexError: list index out of range] bug
#1133 opened Nov 20, 2024 by franhervas99
3 tasks done
2
User-exposed optimiser skipping enhancement good first issue
#1128 opened Nov 14, 2024 by bo3z
Hello, after converting GRU network to IP core using hls4ml, the output of IP core is not always 0. Here is my conversion code. bug
#1111 opened Nov 6, 2024 by yulin3262
5
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