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Description
From stackoverflow question it seems like sign extension not working consistently between interpreter vs verilator or treadle.
Code
import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester}
import chisel3._
class TestTesterUnit(c: Test) extends PeekPokeTester(c) {
val value = 31
poke(c.io.a, value)
poke(c.io.b, 1)
step(1)
expect(c.io.out, value)
}
class TestTester extends ChiselFlatSpec {
for (backendName <- backends) {
"Test" should s"should sign-extended AND operation (with $backendName)" in {
Driver(() => new Test, backendName) {
c => new TestTesterUnit(c)
} should be (true)
}
}
}
class Test extends Module {
val io = IO(new Bundle {
val a = Input(SInt(32.W))
val b = Input(SInt(1.W))
val out = Output(SInt(32.W))
})
io.out := io.a & io.b
}