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gtxzsxxk/veripython

本科编译原理大作业：Verilog to Python Testbench Module：生成 FIRRTL 中间表示的 Verilog 文法子集的前端与基于 Arcilator 生成 Python 仿真模块的后端

python

llvm

verilog

testbench

mlir

• C++
·
• 14
·
• Updated
  on Jan 8

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