Any plans to support STM32N6?

[iabdalkader]

Hi!

Are there any plans to add support for the STM32N6? It uses the same IP (DCW2) as the F7, H7, etc., with an on-chip HS PHY, though I’m not sure about the revision. I have a simple patch that works well enough (with additional code in my application to enable the PHY clock, etc.), but it only works for me in FS mode. I was wondering if there’s interest in adding proper support for this—if it’s even needed. I could probably submit it but could use some help, or I could provide help with testing.

diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 0a4462a0a..13333b421 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -217,6 +217,12 @@
 
   #define TUP_DCD_ENDPOINT_MAX    9
 
+#elif TU_CHECK_MCU(OPT_MCU_STM32N6)
+  #define TUP_USBIP_DWC2
+  #define TUP_USBIP_DWC2_STM32
+
+  #define TUP_DCD_ENDPOINT_MAX    9
+
 #elif TU_CHECK_MCU(OPT_MCU_STM32H5)
   #define TUP_USBIP_FSDEV
   #define TUP_USBIP_FSDEV_STM32
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index 3237a50f6..9fbfe92b0 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -69,6 +69,21 @@ extern "C" {
     #define OTG_FS_IRQn             OTG_HS_IRQn
   #endif
 
+#elif CFG_TUSB_MCU == OPT_MCU_STM32N6
+  #include "stm32n6xx.h"
+
+  #define EP_MAX_FS       9
+  #define EP_FIFO_SIZE_FS 4096
+
+  #define EP_MAX_HS       9
+  #define EP_FIFO_SIZE_HS 4096
+
+  #define USB_OTG_FS_PERIPH_BASE  USB1_OTG_HS_BASE
+  #define OTG_FS_IRQn             USB1_OTG_HS_IRQn
+
+  #define USB_OTG_HS_PERIPH_BASE  USB1_OTG_HS_BASE
+  #define OTG_HS_IRQn             USB1_OTG_HS_IRQn
+
 #elif CFG_TUSB_MCU == OPT_MCU_STM32F7
   #include "stm32f7xx.h"
   #define EP_MAX_FS       6
diff --git a/src/tusb_option.h b/src/tusb_option.h
index fb0209023..8c22fecaa 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -91,6 +91,7 @@
 #define OPT_MCU_STM32U5           313 ///< ST U5
 #define OPT_MCU_STM32L5           314 ///< ST L5
 #define OPT_MCU_STM32H5           315 ///< ST H5
+#define OPT_MCU_STM32N6           316 ///< ST N6
 
 // Sony
 #define OPT_MCU_CXD56             400 ///< SONY CXD56

[HiFiPhile]

Hi,

Thank you for your interest. None of maintainers have the board yet, you can make a PR if you want.

[james-advatek]

I have been working on a port for the N6 (specifically the nucleo board, but I do also have the DK). It currently is working for the cdc_dual_ports example in HS mode, but I might need some help to ensure it is consistent with the other STM32 ports. @HiFiPhile I heavily based my port around your H7RS port, but I had to enable the Cortex M security extension compiler option to get it building as a first stage boot loader. This didn't seem to be needed for the STM32U5 ports however, and I possibly don't need to enable the MPU or RISAF (I haven't tested this yet).

It also appears as though the N6 utilises the 'PCD' drivers when operating as a device, and 'HCD' drivers when operating as a host, which I'm not sure if there is any prior examples of.

EDIT: I've now tested the USB Host capabilities which also seems to be working (tested the host/device_info example).