Feature Request: Ability of import precompiled Iverilog netlist as an external file.

[3478t784dfsi]

The current Digital version recompiles all the Verilog code in the design every time an Icarus Verilog simulation is executed, storing the resulting netlist in a randomly named folder under /tmp.
If the design includes complex logic — for example, the code below uses a large number of registers — this process can be time-consuming. Consider the following 16-bit memory module:

module memory_16bit (
    input        clk,
    input        we,            // Write enable
    input        oe,            // Output enable
    input [15:0] addr,          // Address input
    input [15:0] din,           // Data input
    input        width_ext,     // 0: 8-bit read, 1: 16-bit read
    output reg [15:0] dout      // Data output
);

// 64KB memory, 8-bit width
reg [7:0] mem [0:65535];

// Handle address increment with wrap-around
wire [15:0] next_addr = (addr == 16'hFFFF) ? 16'h0000 : addr + 1;

always @(posedge clk) begin
    if (we) begin
        mem[addr] <= din;  // Write data
    end

    // By default, dout is not updated unless reading
end

always @(*) begin
    if (oe) begin
        case (width_ext)
            1'b0: begin // 8-bit read: read only the current byte
                // The LSB of the address determines low or high byte
                if (addr[0] == 1'b0) begin
                    dout = {8'h00, mem[addr][7:0]}; // Low byte
                end else begin
                    dout = {8'h00, mem[addr][15:8]}; // High byte
                end
            end

            1'b1: begin // 16-bit read: current and next address
                dout = {mem[addr][15:8], mem[next_addr][7:0]};
            end

            default: dout = 16'h0;
        endcase
    end else begin
        dout = 16'hz; // High impedance
    end
end

endmodule

This process consumes 3 to 4 min (on intel xeon E3-1220) . If simulations need to be run multiple times, this results in repeated and unnecessary compilation delays. Therefore, I would like the option to "use a precompiled netlist file" to be available when importing an external Verilog file.