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Copy file name to clipboardExpand all lines: llvm/docs/ReleaseNotes.rst
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@@ -108,16 +108,18 @@ Changes to the AArch64 Backend
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* Added support for Cortex-A65, Cortex-A65AE, Neoverse E1 and Neoverse N1 cores.
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* With a few more bugs fixed in the LLVM 10 release, clang-cl can now target windows-on-Arm well, demonstrated by building complex pieces of software such as Chromium and the Electron framework.
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* With a few more bugs fixed in the LLVM 10 release, clang-cl can now target
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Windows-on-ARM well, demonstrated by building complex pieces of software such
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as Chromium and the Electron framework.
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* Support for -fpatchable-function-entry was added.
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* Support for ``-fpatchable-function-entry`` was added.
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Changes to the ARM Backend
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--------------------------
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* Optimized Armv8.1-M code generation, including generating Low Overhead Loops.
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* Optimized ARMv8.1-M code generation, including generating Low Overhead Loops.
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* Added auto-vectorization for the Armv8.1-M MVE vector extension.
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* Added auto-vectorization for the ARMv8.1-M MVE vector extension.
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* Support was added for inline asm constraints s,j,x,N,O.
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@@ -160,7 +162,7 @@ Optimization:
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* Enabled vectorization of math routines on PowerPC using MASSV (Mathematical Acceleration SubSystem) library
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copiler-rt:
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compiler-rt:
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* Added/improved conversion functions from IBM long double to 128-bit integers
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@@ -211,12 +213,13 @@ Changes to the X86 Target
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* v32i8 and v64i8 vectors with AVX512F enabled, but AVX512BW disabled will now
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be passed in ZMM registers for calls and returns. Previously they were passed
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in two YMM registers. Old behavior can be enabled by passing
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-x86-enable-old-knl-abi
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``-x86-enable-old-knl-abi``.
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* -mprefer-vector-width=256 is now the default behavior skylake-avx512 and later
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Intel CPUs. This tries to limit the use of 512-bit registers which can cause a
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decrease in CPU frequency on these CPUs. This can be re-enabled by passing
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-mprefer-vector-width=512 to clang or passing -mattr=-prefer-256-bit to llc.
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* ``-mprefer-vector-width=256`` is now the default behavior skylake-avx512 and
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later Intel CPUs. This tries to limit the use of 512-bit registers which can
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cause a decrease in CPU frequency on these CPUs. This can be re-enabled by
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passing ``-mprefer-vector-width=512`` to clang or passing
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``-mattr=-prefer-256-bit`` to llc.
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* Deprecated the mpx feature flag for the Intel MPX instructions. There were no
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intrinsics for this feature. This change only this effects the results
@@ -231,7 +234,7 @@ Changes to the X86 Target
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Changes to the WebAssembly Target
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---------------------------------
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* __attribute__((used)) no longer implies that a symbol is exported, for
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* ``__attribute__((used))`` no longer implies that a symbol is exported, for
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consistency with other targets.
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* Multivalue function signatures are now supported in WebAssembly object files
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* There have been some small changes to the code generation for atomic
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operations.
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* RISC-V no longer emits incorrect CFI directives in function prologs and
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epilogs.
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* RISC-V no longer emits incorrect CFI directives in function prologues and
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epilogues.
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* RV64 no longer clears the upper bits when returning complex types from
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libcalls using the LP64 psABI.
@@ -339,7 +342,7 @@ Compiler-RT:
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* RISC-V (both 64-bit and 32-bit) is now supported by compiler-rt, allowing
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crtbegin and crtend to be built.
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* The Sanitizers now support 64-bit RISC-V on linux.
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* The Sanitizers now support 64-bit RISC-V on Linux.
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