[rvfi] Refactoring how we capture async signals

In a scenario where we capture an IRQ and wait to send it with
a RVFI package, we stop sampling for other signals (e.g. Debug Req)
This makes it hard to find/fix cosimulation bugs so this commit
changes that structure to be more flexible for each signal.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>

Author: ctopal

rtl/ibex_core.sv

@@ -1176,7 +1176,9 @@ module ibex_core import ibex_pkg::*; #(
   ibex_pkg::irqs_t captured_mip;
   logic            captured_nmi;
   logic            captured_debug_req;
-  logic            captured_valid;
+  logic            captured_valid_nmi;
+  logic            captured_valid_irq;
+  logic            captured_valid_dbg;
 
   // RVFI extension for co-simulation support
   // debug_req and MIP captured at IF -> ID transition so one extra stage
@@ -1321,23 +1323,33 @@ module ibex_core import ibex_pkg::*; #(
 
   always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
-      captured_valid     <= 1'b0;
+      captured_valid_nmi     <= 1'b0;
+      captured_valid_irq     <= 1'b0;
+      captured_valid_dbg     <= 1'b0;
       captured_mip       <= '0;
       captured_nmi       <= 1'b0;
       captured_debug_req <= 1'b0;
     end else  begin
       // Capture when ID stage has emptied out and something occurs that will cause a trap and we
       // haven't yet captured
-      if (~instr_valid_id & (new_debug_req | new_irq | new_nmi) & ~captured_valid) begin
-        captured_valid     <= 1'b1;
+      if (~instr_valid_id & new_nmi & ~captured_valid_nmi) begin
+        captured_valid_nmi <= 1'b1;
         captured_nmi       <= irq_nm_i;
+      end
+      if (~instr_valid_id & new_irq & ~captured_valid_irq) begin
+        captured_valid_irq <= 1'b1;
         captured_mip       <= cs_registers_i.mip;
+      end
+      if (~instr_valid_id & new_debug_req & ~captured_valid_dbg) begin
+        captured_valid_dbg <= 1'b1;
         captured_debug_req <= debug_req_i;
       end
 
       // Capture cleared out as soon as a new instruction appears in ID
       if (if_stage_i.instr_valid_id_d) begin
-        captured_valid <= 1'b0;
+        captured_valid_nmi     <= 1'b0;
+        captured_valid_irq     <= 1'b0;
+        captured_valid_dbg     <= 1'b0;
       end
     end
   end
@@ -1354,12 +1366,12 @@ module ibex_core import ibex_pkg::*; #(
       rvfi_ext_stage_nmi[0]       <= '0;
       rvfi_ext_stage_debug_req[0] <= '0;
     end else if (if_stage_i.instr_valid_id_d & if_stage_i.instr_new_id_d) begin
-      rvfi_ext_stage_mip[0]       <= instr_valid_id | ~captured_valid ? cs_registers_i.mip :
-                                                                        captured_mip;
-      rvfi_ext_stage_nmi[0]       <= instr_valid_id | ~captured_valid ? irq_nm_i :
-                                                                        captured_nmi;
-      rvfi_ext_stage_debug_req[0] <= instr_valid_id | ~captured_valid ? debug_req_i        :
-                                                                        captured_debug_req;
+      rvfi_ext_stage_mip[0]       <= instr_valid_id | ~captured_valid_irq ? cs_registers_i.mip :
+                                                                            captured_mip;
+      rvfi_ext_stage_nmi[0]       <= instr_valid_id | ~captured_valid_nmi ? irq_nm_i :
+                                                                            captured_nmi;
+      rvfi_ext_stage_debug_req[0] <= instr_valid_id | ~captured_valid_dbg ? debug_req_i        :
+                                                                            captured_debug_req;
     end
   end