[dv] Add coverpoints for dummy instructions in each stage

Signed-off-by: Andreas Kurth <adk@lowrisc.org>

Author: andreaskurth

doc/03_reference/coverage_plan.rst

@@ -315,6 +315,12 @@ For more detail about each security countermeasure in Ibex see :ref:`security`
 
 * ``cp_dummy_instr`` - Executing each instruction category while dummy instruction insertion feature is enabled.
 
+* ``cp_dummy_instr_if_stage`` - The IF stage handles a dummy instruction.
+
+* ``cp_dummy_instr_id_stage`` - The ID/EX stage handles a dummy instruction.
+
+* ``cp_dummy_instr_wb_stage`` - The WB stage handles a dummy instruction.
+
 * ``cp_rf_a_ecc_err``, ``cp_rf_b_ecc_err`` - Register file integrity (ECC) fault is seen for port A/B.
 
 * ``cp_icache_ecc_err`` - ICache has seen an integrity (ECC) fault.

dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv

@@ -447,6 +447,11 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
       illegal_bins illegal = {InstrCategoryOther, InstrCategoryOtherIllegal};
     }
 
+    // Each stage sees a dummy instruction.
+    cp_dummy_instr_if_stage: coverpoint if_stage_i.fcov_insert_dummy_instr;
+    cp_dummy_instr_id_stage: coverpoint if_stage_i.dummy_instr_id_o;
+    cp_dummy_instr_wb_stage: coverpoint wb_stage_i.dummy_instr_wb_o;
+
     cp_rf_a_ecc_err: coverpoint fcov_rf_ecc_err_a_id;
     cp_rf_b_ecc_err: coverpoint fcov_rf_ecc_err_b_id;
 

rtl/ibex_if_stage.sv

@@ -689,6 +689,8 @@ module ibex_if_stage import ibex_pkg::*; #(
   // fcov signals for V2S
   `DV_FCOV_SIGNAL_GEN_IF(logic [1:0], dummy_instr_type,
     gen_dummy_instr.dummy_instr_i.lfsr_data.instr_type, DummyInstructions)
+  `DV_FCOV_SIGNAL_GEN_IF(logic, insert_dummy_instr,
+    gen_dummy_instr.insert_dummy_instr, DummyInstructions)
 `endif
 
   ////////////////