[dv] Don't set rvfi_trap when executing ebreak into debug

This aids the implementation of the double fault detector checker (as an
ebreak into debug doesn't sync the seen_sync_exec flag).

Author: GregAC

dv/cosim/spike_cosim.cc

@@ -954,10 +954,10 @@ bool SpikeCosim::check_debug_ebreak(uint32_t write_reg, uint32_t pc,
     return false;
   }
 
-  if (!sync_trap) {
+  if (sync_trap) {
     std::stringstream err_str;
-    err_str << "DUT executed ebreak at " << std::hex << pc
-            << " but didn't indicate a synchronous trap, which was unexpected";
+    err_str << "DUT executed ebreak into debug at " << std::hex << pc
+            << " but indicated a synchronous trap, which was unexpected";
     errors.emplace_back(err_str.str());
 
     return false;

rtl/ibex_core.sv

@@ -1345,7 +1345,9 @@ module ibex_core import ibex_pkg::*; #(
       end
     end
 
-    assign rvfi_trap_id = id_stage_i.controller_i.id_exception_o;
+    assign rvfi_trap_id = id_stage_i.controller_i.id_exception_o &
+      ~(id_stage_i.ebrk_insn & id_stage_i.controller_i.ebreak_into_debug);
+
     assign rvfi_trap_wb = id_stage_i.controller_i.exc_req_lsu;
     // WB is instantly done in the tracking pipeline when a trap is progress through the pipeline
     assign rvfi_wb_done = rvfi_stage_valid[0] & (instr_done_wb | rvfi_stage_trap[0]);
@@ -1356,7 +1358,9 @@ module ibex_core import ibex_pkg::*; #(
     // Without writeback stage signal new instr_new_wb when instruction enters ID/EX to correctly
     // setup register write signals
     assign rvfi_instr_new_wb = instr_new_id;
-    assign rvfi_trap_id = id_stage_i.controller_i.exc_req_d | id_stage_i.controller_i.exc_req_lsu;
+    assign rvfi_trap_id =
+      (id_stage_i.controller_i.exc_req_d | id_stage_i.controller_i.exc_req_lsu) &
+      ~(id_stage_i.ebrk_insn & id_stage_i.controller_i.ebreak_into_debug);
     assign rvfi_trap_wb = 1'b0;
     assign rvfi_wb_done = instr_done_wb;
   end