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[rtl] Refactor register files to bring common logic together #2217

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@GregAC

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@GregAC

We have 3 register file implementations, one flip-flop based, one latch based and one targetting FPGA implementation. They all duplicate various bits of security hardening logic. The register files should be refactored so the security hardening logic is in a common module as much as is possible and keeping the per-implementation logic to a minimum.

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