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Description
Observed Behavior
I encountered some cosim mismatches around operations on CSR instret (user mode delegate of minstret), which is not (planned to be) implemented (according to #1973 ).
FAILURE: Co-simulation mismatch at time 36
PC mismatch, DUT retired : 100000 , but the ISS retired: 100008
[36] %Error: ibex_simple_system_cosim_checker.sv:74: Assertion failed in TOP.ibex_simple_system.u_ibex_simple_system_cosim_checker_bind: Co-simulation mismatch seen
Received stop request, shutting down simulation.
trace_core_00000000.log:
Time Cycle PC Insn Decoded instruction Register and memory contents
30 11 00100004 c0206073 csrrsi x0,instret,0 x0=0x00000000
=> trap IllegalInsn here
36 14 00100000 0670 c.addi4spn x12,x2,780 x12=0x0000030c
Expected Behavior
As the project has not yet planned to impl Zicntr, spike used as reference model should be aligned.
Currently the fork lowrisc/riscv-isa-sim is far behind the upstream. While the upstream has made Zicntr optional regarding the ISA string, there exists a fragment in the fork that always enable Zicntr:
riscv/isa_parser.cc:L37
// enable zicntr and zihpm unconditionally for backward compatibility
extension_table[EXT_ZICNTR] = true;Steps to reproduce the issue
- Build lowrisc:ibex:ibex_simple_system_cosim
- Run Cosim with the provided testcase binary (which may need conversion? bin is not officially supported, I run with my modified simulating c++ code) build/lowrisc_ibex_ibex_simple_system_cosim_0/sim-verilator/Vibex_simple_system -c 10000 --meminit=ram,errors/ba8335cdf5815390859b835ec904d458
- Mismatch reported
My Environment
EDA tool and version:
Verilator 5.006 2023-01-22 rev (Debian 5.006-3)
Operating system:
Version of the Ibex source code:
master (commit 587e9fe)
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