From cce3e335a686debd932d68e75a9358230aa4fb37 Mon Sep 17 00:00:00 2001 From: Canberk Topal Date: Mon, 7 Nov 2022 19:20:29 +0000 Subject: [PATCH] [dv] Fix how we catch imem_err on bus side. In the case of a load/store access fault trap, rvfi_order number stays same but pc_id changes. And if the older instruction is faulty we still end up pushing it to the queue. This commit fixes that by checking for a matching rvfi_order number first. Signed-off-by: Canberk Topal --- .../common/ibex_cosim_agent/ibex_cosim_scoreboard.sv | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv b/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv index a347b5dd3c..0a89accccc 100644 --- a/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv +++ b/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv @@ -240,8 +240,13 @@ class ibex_cosim_scoreboard extends uvm_scoreboard; forever begin // Wait for new instruction to appear in ID stage wait (instr_vif.instr_cb.valid_id && - instr_vif.instr_cb.instr_new_id && - latest_order != instr_vif.instr_cb.rvfi_order_id); + instr_vif.instr_cb.instr_new_id); + // Determine if we were here before. If so, that means this rvfi_order number was actually used + // twice (a load/store fault caused jumping to the handler). Delete the old iside_error_queue + // element. + if (latest_order == instr_vif.instr_cb.rvfi_order_id) begin + iside_error_queue.pop_back(); + end // Determine if the instruction comes from an address that has seen an error that wasn't a PMP // error (the icache records both PMP errors and fetch errors with the same error bits). If a // fetch error was seen add the instruction order ID and address to iside_error_queue. @@ -264,6 +269,8 @@ class ibex_cosim_scoreboard extends uvm_scoreboard; end latest_order = instr_vif.instr_cb.rvfi_order_id; + + @(posedge instr_vif.clk); end endtask: run_cosim_imem_errors;