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[dv] Fix how we catch iside_err in cosim #1909

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[dv] Fix how we catch iside_err in cosim #1909

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11 changes: 9 additions & 2 deletions dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -240,8 +240,13 @@ class ibex_cosim_scoreboard extends uvm_scoreboard;
forever begin
// Wait for new instruction to appear in ID stage
wait (instr_vif.instr_cb.valid_id &&
instr_vif.instr_cb.instr_new_id &&
latest_order != instr_vif.instr_cb.rvfi_order_id);
instr_vif.instr_cb.instr_new_id);
// Determine if we were here before. If so, that means this rvfi_order number was actually used
// twice (a load/store fault caused jumping to the handler). Delete the old iside_error_queue
// element.
if (latest_order == instr_vif.instr_cb.rvfi_order_id) begin
iside_error_queue.pop_back();
end
Comment on lines +244 to +249
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After a bit of thought, I am not sure if this would work considering we actually don't check for failed_iside_accesses.exists(aligned_addr) && !iside_pmp_failure.exists(aligned_addr) in here. Concern being, we might end up deleting a valid iside_error. I guess the solution would be to check for the condition again before calculating the new aligned_addr, WDYT @GregAC ? Regression numbers show no such problem but just wanted to be sure before merging this.

// Determine if the instruction comes from an address that has seen an error that wasn't a PMP
// error (the icache records both PMP errors and fetch errors with the same error bits). If a
// fetch error was seen add the instruction order ID and address to iside_error_queue.
Expand All @@ -264,6 +269,8 @@ class ibex_cosim_scoreboard extends uvm_scoreboard;
end

latest_order = instr_vif.instr_cb.rvfi_order_id;

@(posedge instr_vif.clk);
end
endtask: run_cosim_imem_errors;

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