HDL Verifier Self-Guided Tutorial

HDL Verifier™ enables you to reuse your system-level design environment in your HDL design environment. You can test and verify RTL designs against golden reference models in MATLAB® and Simulink®, debug designs in third-party simulators or hardware, and generate testbenches and verification IP.

This tutorial is designed to help you learn about three of the most popular features of HDL Verifier: HDL Cosimulation, FPGA-in-the-Loop, and FPGA Data Capture. The tutorial shows you how you can use these features whether you develop HDL on your own or use HDL Coder™ to generate HDL from MATLAB or Simulink.

MathWorks Products (https://www.mathworks.com)

MATLAB release R2022a or newer are required.

• Required products:
  • MATLAB
  • Simulink
  • DSP HDL Toolbox™
  • DSP System Toolbox™
  • Fixed-Point Designer™
  • HDL Coder
  • HDL Verifier
  • MATLAB Coder™
  • Signal Processing Toolbox™
• Required support packages
  • HDL Coder Support Package for AMD FPGA and SoC Devices
  • HDL Verifier Support Package for AMD FPGA and SoC Devices

Third-Party Products

• Required for HDL Cosimulation
  • Siemens® ModelSim™ simulator or
  • Siemens Questa™ simulator
• Required for FPGA-in-the-Loop simulation and FPGA Data Capture
  • AMD® Vivado™
  • Zedboard™ Development kit

Overview

The Tutorial provides instructions to run HDL Cosimulation with MATLAB and Simulink, perform FPGA validation using FPGA-in-the-Loop simulation, and load signals from designs programmed into development boards into MATLAB using FPGA Data Capture. The tutorial has the following sections.

• HDL Cosimulation with Simulink
  • Cosimulation with existing HDL code (i.e., hand-coded RTL workflow)
  • Cosimulation with HDL code generated by HDL Coder
• FPGA-in-the-loop (FIL) with Simulink
  • FPGA-in-the-Loop simulation with existing HDL code (i.e., hand-coded RTL workflow)
  • FPGA-in-the-Loop simulation with HDL code generated by HDL Coder
• FPGA Data Capture
  • Data capture for existing HDL code (i.e., hand-coded RTL workflow)
  • IP core generation workflow that integrates FPGA Data Capture as part of IP core generation in an existing AXI Stream project

Examples are provided throughout the guide to illustrate concepts.

Trademark Notices

MathWorks®, MATLAB®, and Simulink® are registered trademarks of The MathWorks, Inc. DSP HDL Toolbox™, DSP System Toolbox™, Fixed-Point Designer™, HDL Coder™, HDL Verifier™, MATLAB Coder™, and Signal Processing Toolbox™ are trademarks of The MathWorks, Inc.

Siemens® is a registered trademark of Siemens Trademark GmbH & Co. KG. Questa™ and MODELSIM™ are trademarks of Siemens Industry Software, Inc.

AMD® and Xilinx® are registered trademarks of Advanced Micro Devices, Inc. AMD Vivado™ is a trademark of Advanced Micro Devices, Inc.

ZedBoard is a trademark of Avnet, Inc.