From 207dd31f27dd86eb74e166c6706070374ba7e7df Mon Sep 17 00:00:00 2001 From: Jamie Smith Date: Fri, 27 Jun 2025 01:13:11 -0700 Subject: [PATCH 1/3] Ambiq Apollo3: Make SFW_ARTEMIS use arduino uno form factor, fix GPIO IRQ API --- hal/include/hal/gpio_irq_api.h | 1 + .../TARGET_SFE_ARTEMIS/PinNames.h | 100 ++++++++++-------- .../TARGET_Apollo3/device/gpio_irq_api.c | 79 ++++++++++---- .../TARGET_Apollo3/device/objects_gpio.h | 3 + targets/targets.json5 | 5 +- 5 files changed, 125 insertions(+), 63 deletions(-) diff --git a/hal/include/hal/gpio_irq_api.h b/hal/include/hal/gpio_irq_api.h index cb9a40d5c2a..30b11f46232 100644 --- a/hal/include/hal/gpio_irq_api.h +++ b/hal/include/hal/gpio_irq_api.h @@ -49,6 +49,7 @@ typedef void (*gpio_irq_handler)(uintptr_t context, gpio_irq_event event); * # Defined behavior * * ::gpio_irq_init initializes the GPIO IRQ pin * * ::gpio_irq_init attaches the interrupt handler + * * ::gpio_irq_init enables the IRQ * * ::gpio_irq_free releases the GPIO IRQ pin * * ::gpio_irq_set enables/disables pin IRQ event * * ::gpio_irq_enable enables GPIO IRQ diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/PinNames.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/PinNames.h index 55269393883..f4daf825368 100644 --- a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/PinNames.h +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/PinNames.h @@ -39,41 +39,56 @@ extern "C" typedef enum { // Digital naming - D0 = 25, - D1 = 24, - D2 = 35, - D3 = 4, - D4 = 22, - D5 = 23, - D6 = 27, - D7 = 28, - D8 = 32, - D9 = 12, - D10 = 13, - D11 = 7, - D12 = 6, - D13 = 5, - D14 = 40, - D15 = 39, - D16 = 29, - D17 = 11, - D18 = 34, - D19 = 33, - D20 = 16, - D21 = 31, - - // Analog naming - A0 = D16, - A1 = D17, - A2 = D18, - A3 = D19, - A4 = D20, - A5 = D21, - A6 = D2, - // A7 = ?? - A8 = D8, - A9 = D9, - A10 = D10, + p0 = 25, + p1 = 24, + p2 = 35, + p3 = 4, + p4 = 22, + p5 = 23, + p6 = 27, + p7 = 28, + p8 = 32, + p9 = 12, + p10 = 13, + p11 = 7, + p12 = 6, + p13 = 5, + p14 = 40, + p15 = 39, + p16 = 29, + p17 = 11, + p18 = 34, + p19 = 33, + p20 = 16, + p21 = 31, + +#ifdef TARGET_FF_ARDUINO_UNO + // Arduino form factor pins + ARDUINO_UNO_D0 = p0, + ARDUINO_UNO_D1 = p1, + ARDUINO_UNO_D2 = p2, + ARDUINO_UNO_D3 = p3, + ARDUINO_UNO_D4 = p4, + ARDUINO_UNO_D5 = p5, + ARDUINO_UNO_D6 = p6, + ARDUINO_UNO_D7 = p7, + ARDUINO_UNO_D8 = p8, + ARDUINO_UNO_D9 = p9, + ARDUINO_UNO_D10 = p10, + ARDUINO_UNO_D11 = p11, + ARDUINO_UNO_D12 = p12, + ARDUINO_UNO_D13 = p13, + ARDUINO_UNO_D14 = p14, + ARDUINO_UNO_D15 = p15, + + ARDUINO_UNO_A0 = p16, + ARDUINO_UNO_A1 = p17, + ARDUINO_UNO_A2 = p18, + ARDUINO_UNO_A3 = p19, + ARDUINO_UNO_A4 = p20, + ARDUINO_UNO_A5 = p21, + ARDUINO_UNO_A6 = p2, +#endif // UART SERIAL_TX = AM_BSP_PRIM_UART_TX_PIN, @@ -81,26 +96,25 @@ typedef enum CONSOLE_TX = SERIAL_TX, CONSOLE_RX = SERIAL_RX, - SERIAL1_TX = D1, - SERIAL1_RX = D0, + SERIAL1_TX = p1, + SERIAL1_RX = p0, // Not connected NC = NC_VAL } PinName; // LEDs -#define LED1 D13 // Blue LED +#define LED1 p13 // Blue LED // I2C bus -#define I2C_SCL D15 -#define I2C_SDA D14 +// note: I2C_SCL and I2C_SDA defines are provided by the FF_ARDUINO_UNO header #define QWIIC_SCL I2C_SCL #define QWIIC_SDA I2C_SDA // SPI bus -#define SPI_CLK D13 -#define SPI_SDO D11 -#define SPI_SDI D12 +#define SPI_CLK p13 +#define SPI_SDO p11 +#define SPI_SDI p12 #if defined(MBED_CONF_TARGET_STDIO_UART_TX) #define STDIO_UART_TX MBED_CONF_TARGET_STDIO_UART_TX diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/gpio_irq_api.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/gpio_irq_api.c index 2c6f87d2463..2f8639c3493 100644 --- a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/gpio_irq_api.c +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/gpio_irq_api.c @@ -31,6 +31,7 @@ extern "C" { #endif +static void ap3_gpio_update_int_en(gpio_irq_t *obj); uint32_t ap3_gpio_enable_interrupts(uint32_t ui32Pin, am_hal_gpio_intdir_e eIntDir); /** GPIO IRQ HAL structure. gpio_irq_s is declared in the target's HAL */ @@ -70,20 +71,19 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintpt //grab the correct irq control object ap3_gpio_irq_control_t *control = &gpio_irq_control[pin]; - //Register locally + // Register locally control->pad = pin; control->handler = handler; control->id = context; control->events = IRQ_NONE; - //Attach to object + // Attach to object obj->control = control; - //Make sure the interrupt is set to none to reflect the new events value - ap3_gpio_enable_interrupts(control->pad, AM_HAL_GPIO_PIN_INTDIR_NONE); + // Start with the IRQ "enabled", but don't actually enable it till something is attached + obj->irq_requested_enabled = true; - //Enable GPIO IRQ's in the NVIC - gpio_irq_enable(obj); + // Make sure the GPIO IRQ is enabled in NVIC NVIC_SetVector((IRQn_Type)GPIO_IRQn, (uint32_t)am_gpio_isr); NVIC_EnableIRQ((IRQn_Type)GPIO_IRQn); return 0; @@ -99,7 +99,18 @@ void am_gpio_isr(void) if (gpio_int_mask & 0x0000000000000001) { am_hal_gpio_interrupt_clear(AM_HAL_GPIO_BIT(pinNum)); ap3_gpio_irq_control_t irq_ctrl = gpio_irq_control[pinNum]; - ((gpio_irq_handler)irq_ctrl.handler)(irq_ctrl.id, irq_ctrl.events); + + uint8_t event = irq_ctrl.events; + if(event == (IRQ_RISE | IRQ_FALL)) + { + // This pin is configured for both rise and fall events. However, this MCU does not have separate + // status registers for tracking rising/falling interrupts. + // So, read the pin to figure out which interrupt happened. It's not totally foolproof but + // it should work in most cases. + event = am_hal_gpio_input_read(irq_ctrl.pad) ? IRQ_RISE : IRQ_FALL; + } + + ((gpio_irq_handler)irq_ctrl.handler)(irq_ctrl.id, event); } gpio_int_mask >>= 1; pinNum++; @@ -112,6 +123,8 @@ void am_gpio_isr(void) */ void gpio_irq_free(gpio_irq_t *obj) { + // Make sure interrupt can't trigger + gpio_irq_disable(obj); } /** Enable/disable pin IRQ event @@ -121,20 +134,21 @@ void gpio_irq_free(gpio_irq_t *obj) * @param enable The enable flag */ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - //Clear state - obj->control->events &= (~event); +{ if (enable) { - //Reset if enabled obj->control->events |= event; } + else { + obj->control->events &= ~event; + } - // Map enabled events to a value the reflects the ambiq hal/register values + // Map enabled events to a value the reflects the ambiq hal/register values. + // Note that we don't want to actually set INTDIR_NONE, because this disables reading the pin (!!) + // So instead, if asked to disable the IRQ, we leave LO2HIGH interrupt enabled in the PINCFG register but + // don't enable the interrupt for this pin in the register am_hal_gpio_intdir_e ap3_int_dir = 0x00; switch (obj->control->events) { case IRQ_NONE: - ap3_int_dir = AM_HAL_GPIO_PIN_INTDIR_NONE; - break; case IRQ_RISE: ap3_int_dir = AM_HAL_GPIO_PIN_INTDIR_LO2HI; break; @@ -146,7 +160,17 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) break; } + // If switching to NONE, disable the IRQ first + if(obj->control->events == IRQ_NONE) { + ap3_gpio_update_int_en(obj); + } + ap3_gpio_enable_interrupts(obj->control->pad, ap3_int_dir); + + // Otherwise enable IRQ now + if(obj->control->events != IRQ_NONE) { + ap3_gpio_update_int_en(obj); + } } /** Enable GPIO IRQ @@ -156,8 +180,8 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) */ void gpio_irq_enable(gpio_irq_t *obj) { - am_hal_gpio_interrupt_clear(AM_HAL_GPIO_BIT(obj->control->pad)); - am_hal_gpio_interrupt_enable(AM_HAL_GPIO_BIT(obj->control->pad)); + obj->irq_requested_enabled = true; + ap3_gpio_update_int_en(obj); } /** Disable GPIO IRQ @@ -167,11 +191,27 @@ void gpio_irq_enable(gpio_irq_t *obj) */ void gpio_irq_disable(gpio_irq_t *obj) { - am_hal_gpio_interrupt_clear(AM_HAL_GPIO_BIT(obj->control->pad)); - am_hal_gpio_interrupt_disable(AM_HAL_GPIO_BIT(obj->control->pad)); + obj->irq_requested_enabled = false; + ap3_gpio_update_int_en(obj); } /**@}*/ + +// Based on the enabled events and irq_requested_enabled, enable or disable the IRQ +static void ap3_gpio_update_int_en(gpio_irq_t *obj) +{ + if(obj->irq_requested_enabled && obj->control->events != IRQ_NONE) { + // Enable! + am_hal_gpio_interrupt_clear(AM_HAL_GPIO_BIT(obj->control->pad)); + am_hal_gpio_interrupt_enable(AM_HAL_GPIO_BIT(obj->control->pad)); + } + else { + // Disable + am_hal_gpio_interrupt_disable(AM_HAL_GPIO_BIT(obj->control->pad)); + } +} + + uint32_t ap3_gpio_enable_interrupts(uint32_t ui32Pin, am_hal_gpio_intdir_e eIntDir) { uint32_t ui32Padreg, ui32AltPadCfg, ui32GPCfg; @@ -208,7 +248,8 @@ uint32_t ap3_gpio_enable_interrupts(uint32_t ui32Pin, am_hal_gpio_intdir_e eIntD ui32GPCfgShft = ((ui32Pin & 0x7) << 2); - ui32GPCfgAddr = AM_REGADDR(GPIO, CFGA) + ((ui32Pin >> 1) & ~0x3); + // 8 pins per register, and each register is 32 bits wide + ui32GPCfgAddr = AM_REGADDR(GPIO, CFGA) + (ui32Pin / 8) * sizeof(uint32_t); ui32GPCfgClearMask = ~((uint32_t)0xF << ui32GPCfgShft); diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_gpio.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_gpio.h index 67685c3fec8..3513621f2b5 100644 --- a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_gpio.h +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_gpio.h @@ -27,6 +27,8 @@ #include "am_hal_gpio.h" #include "PinNames.h" +#include + #ifdef __cplusplus extern "C" { @@ -124,6 +126,7 @@ typedef struct ap3_gpio_irq_control_t { typedef struct gpio_irq_s { ap3_gpio_irq_control_t *control; + bool irq_requested_enabled; } gpio_irq_s; #define AP3_PINCFG_FUNCSEL_GPIO 3 diff --git a/targets/targets.json5 b/targets/targets.json5 index 6efc5bca4f3..4b4c7102e41 100644 --- a/targets/targets.json5 +++ b/targets/targets.json5 @@ -9728,7 +9728,10 @@ mode is recommended for target MCUs with small amounts of flash and RAM.", }, "SFE_ARTEMIS": { // AKA SparkFun RedBoard Artemis "inherits": ["AMA3B1KK"], - "image_url": "https://cdn.sparkfun.com/r/455-455/assets/parts/1/4/0/1/9/15444-SparkFun_RedBoard_Artemis-01.jpg" + "image_url": "https://cdn.sparkfun.com/r/455-455/assets/parts/1/4/0/1/9/15444-SparkFun_RedBoard_Artemis-01.jpg", + "supported_form_factors": [ + "ARDUINO_UNO" + ] }, "SFE_ARTEMIS_ATP": { // AKA SparkFun RedBoard Artemis ATP "inherits": ["AMA3B1KK"], From a39218484e0a77f4823a8f4514ccc2aacba23ba5 Mon Sep 17 00:00:00 2001 From: Jamie Smith Date: Wed, 2 Jul 2025 09:56:48 -0700 Subject: [PATCH 2/3] Start updating all PinNames.h files for Apollo3 to new standard --- .../TARGET_SFE_ARTEMIS/PinNames.h | 135 ++++++++----- .../TARGET_SFE_ARTEMIS_ATP/PinNames.h | 184 +++++++++++------- .../TARGET_SFE_ARTEMIS_DK/PinNames.h | 152 ++++++++++----- .../TARGET_SFE_ARTEMIS_MODULE/PinNames.h | 115 +++++------ 4 files changed, 353 insertions(+), 233 deletions(-) diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/PinNames.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/PinNames.h index f4daf825368..30e91115272 100644 --- a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/PinNames.h +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/PinNames.h @@ -38,56 +38,85 @@ extern "C" typedef enum { - // Digital naming - p0 = 25, - p1 = 24, - p2 = 35, - p3 = 4, - p4 = 22, - p5 = 23, - p6 = 27, - p7 = 28, - p8 = 32, - p9 = 12, - p10 = 13, - p11 = 7, - p12 = 6, - p13 = 5, - p14 = 40, - p15 = 39, - p16 = 29, - p17 = 11, - p18 = 34, - p19 = 33, - p20 = 16, - p21 = 31, + // Apollo3 I/O pins - CSP and BGA packages + IO_0 = 0, + IO_1 = 1, + IO_2 = 2, + IO_3 = 3, + IO_4 = 4, + IO_5 = 5, + IO_6 = 6, + IO_7 = 7, + IO_8 = 8, + IO_9 = 9, + IO_10 = 10, + IO_11 = 11, + IO_12 = 12, + IO_13 = 13, + IO_14 = 14, + IO_15 = 15, + IO_16 = 16, + IO_17 = 17, + IO_18 = 18, + IO_19 = 19, + IO_20 = 20, + IO_21 = 21, + IO_22 = 22, + IO_23 = 23, + IO_24 = 24, + IO_25 = 25, + IO_26 = 26, + IO_27 = 27, + IO_28 = 28, + IO_29 = 29, + IO_39 = 39, + IO_40 = 40, + IO_41 = 41, + IO_44 = 44, + IO_47 = 47, + IO_48 = 48, + IO_49 = 49, + + // Apollo3 I/O pins - BGA package only + IO_30 = 30, + IO_31 = 31, + IO_32 = 32, + IO_33 = 33, + IO_34 = 34, + IO_35 = 35, + IO_36 = 36, + IO_37 = 37, + IO_38 = 38, + IO_42 = 42, + IO_43 = 43, + IO_45 = 45, + IO_46 = 46, #ifdef TARGET_FF_ARDUINO_UNO // Arduino form factor pins - ARDUINO_UNO_D0 = p0, - ARDUINO_UNO_D1 = p1, - ARDUINO_UNO_D2 = p2, - ARDUINO_UNO_D3 = p3, - ARDUINO_UNO_D4 = p4, - ARDUINO_UNO_D5 = p5, - ARDUINO_UNO_D6 = p6, - ARDUINO_UNO_D7 = p7, - ARDUINO_UNO_D8 = p8, - ARDUINO_UNO_D9 = p9, - ARDUINO_UNO_D10 = p10, - ARDUINO_UNO_D11 = p11, - ARDUINO_UNO_D12 = p12, - ARDUINO_UNO_D13 = p13, - ARDUINO_UNO_D14 = p14, - ARDUINO_UNO_D15 = p15, - - ARDUINO_UNO_A0 = p16, - ARDUINO_UNO_A1 = p17, - ARDUINO_UNO_A2 = p18, - ARDUINO_UNO_A3 = p19, - ARDUINO_UNO_A4 = p20, - ARDUINO_UNO_A5 = p21, - ARDUINO_UNO_A6 = p2, + ARDUINO_UNO_D0 = IO_25, + ARDUINO_UNO_D1 = IO_24, + ARDUINO_UNO_D2 = IO_35, + ARDUINO_UNO_D3 = IO_4, + ARDUINO_UNO_D4 = IO_22, + ARDUINO_UNO_D5 = IO_23, + ARDUINO_UNO_D6 = IO_27, + ARDUINO_UNO_D7 = IO_28, + ARDUINO_UNO_D8 = IO_32, + ARDUINO_UNO_D9 = IO_12, + ARDUINO_UNO_D10 = IO_13, + ARDUINO_UNO_D11 = IO_7, + ARDUINO_UNO_D12 = IO_6, + ARDUINO_UNO_D13 = IO_5, + ARDUINO_UNO_D14 = IO_40, + ARDUINO_UNO_D15 = IO_39, + + ARDUINO_UNO_A0 = IO_29, + ARDUINO_UNO_A1 = IO_11, + ARDUINO_UNO_A2 = IO_34, + ARDUINO_UNO_A3 = IO_33, + ARDUINO_UNO_A4 = IO_16, + ARDUINO_UNO_A5 = IO_31, #endif // UART @@ -96,15 +125,15 @@ typedef enum CONSOLE_TX = SERIAL_TX, CONSOLE_RX = SERIAL_RX, - SERIAL1_TX = p1, - SERIAL1_RX = p0, + SERIAL1_TX = IO_24, + SERIAL1_RX = IO_25, // Not connected NC = NC_VAL } PinName; // LEDs -#define LED1 p13 // Blue LED +#define LED1 IO_5 // Blue LED // I2C bus // note: I2C_SCL and I2C_SDA defines are provided by the FF_ARDUINO_UNO header @@ -112,9 +141,9 @@ typedef enum #define QWIIC_SDA I2C_SDA // SPI bus -#define SPI_CLK p13 -#define SPI_SDO p11 -#define SPI_SDI p12 +#define SPI_SCLK IO_5 +#define SPI_MOSI IO_7 +#define SPI_MISO IO_6 #if defined(MBED_CONF_TARGET_STDIO_UART_TX) #define STDIO_UART_TX MBED_CONF_TARGET_STDIO_UART_TX diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/PinNames.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/PinNames.h index 4ee01c45e26..24e2686fb06 100644 --- a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/PinNames.h +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/PinNames.h @@ -38,53 +38,110 @@ extern "C" typedef enum { + // Apollo3 I/O pins - CSP and BGA packages + IO_0 = 0, + IO_1 = 1, + IO_2 = 2, + IO_3 = 3, + IO_4 = 4, + IO_5 = 5, + IO_6 = 6, + IO_7 = 7, + IO_8 = 8, + IO_9 = 9, + IO_10 = 10, + IO_11 = 11, + IO_12 = 12, + IO_13 = 13, + IO_14 = 14, + IO_15 = 15, + IO_16 = 16, + IO_17 = 17, + IO_18 = 18, + IO_19 = 19, + IO_20 = 20, + IO_21 = 21, + IO_22 = 22, + IO_23 = 23, + IO_24 = 24, + IO_25 = 25, + IO_26 = 26, + IO_27 = 27, + IO_28 = 28, + IO_29 = 29, + IO_39 = 39, + IO_40 = 40, + IO_41 = 41, + IO_44 = 44, + IO_47 = 47, + IO_48 = 48, + IO_49 = 49, + + // Apollo3 I/O pins - BGA package only + IO_30 = 30, + IO_31 = 31, + IO_32 = 32, + IO_33 = 33, + IO_34 = 34, + IO_35 = 35, + IO_36 = 36, + IO_37 = 37, + IO_38 = 38, + IO_42 = 42, + IO_43 = 43, + IO_45 = 45, + IO_46 = 46, + // Digital naming - D0 = 0, - D1 = 1, - D2 = 2, - D3 = 3, - D4 = 4, - D5 = 5, - D6 = 6, - D7 = 7, - D8 = 8, - D9 = 9, - D10 = 10, - D11 = 11, - D12 = 12, - D13 = 13, - D14 = 14, - D15 = 15, - D16 = 16, - D17 = 17, - D18 = 18, - D19 = 19, - // D20 = ?? - // D21 = ?? - D22 = 22, - D23 = 23, - D24 = 24, - D25 = 25, - D26 = 26, - D27 = 27, - D28 = 28, - D29 = 29, - // D30 = ?? - D31 = 31, - D32 = 32, - D33 = 33, - D34 = 34, - D35 = 35, - D36 = 36, - D37 = 37, - D38 = 38, - D39 = 39, - D40 = 40, - D41 = 41, - D42 = 42, - D43 = 43, - D44 = 44, - D45 = 45, + D0 = IO_0, + D1 = IO_1, + D2 = IO_2, + D3 = IO_3, + D4 = IO_4, + D5 = IO_5, + D6 = IO_6, + D7 = IO_7, + D8 = IO_8, + D9 = IO_9, + D10 = IO_10, + D11 = IO_11, + D12 = IO_12, + D13 = IO_13, + D14 = IO_14, + D15 = IO_15, + D16 = IO_16, + D17 = IO_17, + D18 = IO_18, + D19 = IO_19, + + // D20 and D21 used as SWD debug pins, not broken out + + D22 = IO_22, + D23 = IO_23, + D24 = IO_24, + D25 = IO_25, + D26 = IO_26, + D27 = IO_27, + D28 = IO_28, + D29 = IO_29, + + // D30 not broken out from Artemis module + + D31 = IO_31, + D32 = IO_32, + D33 = IO_33, + D34 = IO_34, + D35 = IO_35, + D36 = IO_36, + D37 = IO_37, + D38 = IO_38, + D39 = IO_39, + D40 = IO_40, + D41 = IO_41, + D42 = IO_42, + D43 = IO_43, + D44 = IO_44, + D45 = IO_45, // Analog naming A11 = D11, @@ -98,26 +155,6 @@ typedef enum A34 = D34, A35 = D35, - // LEDs - LED_BLUE = AM_BSP_GPIO_LED_BLUE, - - // mbed original LED naming - LED1 = AM_BSP_GPIO_LED0, - LED2 = D42, - - // I2C - I2C_SCL = AM_BSP_QWIIC_I2C_SCL_PIN, - I2C_SDA = AM_BSP_QWIIC_I2C_SDA_PIN, - - // Qwiic - QWIIC_SCL = I2C_SCL, - QWIIC_SDA = I2C_SDA, - - // SPI - SPI_CLK = AM_BSP_PRIM_SPI_CLK_PIN, - SPI_SDO = AM_BSP_PRIM_SPI_SDO_PIN, - SPI_SDI = AM_BSP_PRIM_SPI_SDI_PIN, - // UART SERIAL_TX = AM_BSP_PRIM_UART_TX_PIN, SERIAL_RX = AM_BSP_PRIM_UART_RX_PIN, @@ -131,6 +168,21 @@ typedef enum NC = NC_VAL } PinName; +// LEDs +#define LED1 IO_5 // Blue LED + +// I2C bus +#define I2C_SCL IO_39 +#define I2C_SDA IO_40 + +#define QWIIC_SCL I2C_SCL +#define QWIIC_SDA I2C_SDA + +// SPI bus +#define SPI_SCLK IO_5 +#define SPI_MOSI IO_7 +#define SPI_MISO IO_6 + #if defined(MBED_CONF_TARGET_STDIO_UART_TX) #define STDIO_UART_TX MBED_CONF_TARGET_STDIO_UART_TX #else diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/PinNames.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/PinNames.h index 56ede1b5cf5..d8da27c3180 100644 --- a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/PinNames.h +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/PinNames.h @@ -38,32 +38,85 @@ extern "C" typedef enum { + // Apollo3 I/O pins - CSP and BGA packages + IO_0 = 0, + IO_1 = 1, + IO_2 = 2, + IO_3 = 3, + IO_4 = 4, + IO_5 = 5, + IO_6 = 6, + IO_7 = 7, + IO_8 = 8, + IO_9 = 9, + IO_10 = 10, + IO_11 = 11, + IO_12 = 12, + IO_13 = 13, + IO_14 = 14, + IO_15 = 15, + IO_16 = 16, + IO_17 = 17, + IO_18 = 18, + IO_19 = 19, + IO_20 = 20, + IO_21 = 21, + IO_22 = 22, + IO_23 = 23, + IO_24 = 24, + IO_25 = 25, + IO_26 = 26, + IO_27 = 27, + IO_28 = 28, + IO_29 = 29, + IO_39 = 39, + IO_40 = 40, + IO_41 = 41, + IO_44 = 44, + IO_47 = 47, + IO_48 = 48, + IO_49 = 49, + + // Apollo3 I/O pins - BGA package only + IO_30 = 30, + IO_31 = 31, + IO_32 = 32, + IO_33 = 33, + IO_34 = 34, + IO_35 = 35, + IO_36 = 36, + IO_37 = 37, + IO_38 = 38, + IO_42 = 42, + IO_43 = 43, + IO_45 = 45, + IO_46 = 46, + // Digital naming - D13 = 13, - D16 = 16, - D23 = 23, - D24 = 24, - D25 = 25, - D26 = 26, - D27 = 27, - D28 = 28, - D29 = 29, - // D30 = 30, ?? - D31 = 31, - D32 = 32, - D33 = 33, - D34 = 34, - D35 = 35, - D36 = 36, - D37 = 37, - D38 = 38, - D39 = 39, - D40 = 40, - D41 = 41, - D42 = 42, - D43 = 43, - D44 = 44, - D45 = 45, + D13 = IO_13, + D16 = IO_16, + D23 = IO_23, + D24 = IO_24, + D25 = IO_25, + D26 = IO_26, + D27 = IO_27, + D28 = IO_28, + D29 = IO_29, + D31 = IO_31, + D32 = IO_32, + D33 = IO_33, + D34 = IO_34, + D35 = IO_35, + D36 = IO_36, + D37 = IO_37, + D38 = IO_38, + D39 = IO_39, + D40 = IO_40, + D41 = IO_41, + D42 = IO_42, + D43 = IO_43, + D44 = IO_44, + D45 = IO_45, // Analog naming A13 = D13, @@ -75,34 +128,6 @@ typedef enum A34 = D34, A35 = D35, - // LEDs - LED_BLUE = AM_BSP_GPIO_LED_BLUE, - - // mbed original LED naming - LED1 = AM_BSP_GPIO_LED0, - LED2 = D24, - - // I2C - I2C_SCL = AM_BSP_QWIIC_I2C_SCL_PIN, - I2C_SDA = AM_BSP_QWIIC_I2C_SDA_PIN, - - // Qwiic - QWIIC_SCL = I2C_SCL, - QWIIC_SDA = I2C_SDA, - - // Accelerometer - ACC_SCL = QWIIC_SCL, - ACC_SDA = QWIIC_SDA, - - // Camera - CAM_SCL = QWIIC_SCL, - CAM_SDA = QWIIC_SDA, - - // SPI - SPI_CLK = AM_BSP_PRIM_SPI_CLK_PIN, - SPI_SDO = AM_BSP_PRIM_SPI_SDO_PIN, - SPI_SDI = AM_BSP_PRIM_SPI_SDI_PIN, - // UART SERIAL_TX = AM_BSP_PRIM_UART_TX_PIN, SERIAL_RX = AM_BSP_PRIM_UART_RX_PIN, @@ -113,6 +138,27 @@ typedef enum NC = NC_VAL } PinName; +// LEDs +#define LED1 IO_23 // Blue LED + +// I2C bus +#define I2C_SCL IO_8 +#define I2C_SDA IO_9 + +#define QWIIC_SCL I2C_SCL +#define QWIIC_SDA I2C_SDA + +#define ACC_SCL QWIIC_SCL +#define ACC_SDA QWIIC_SDA + +#define CAM_SCL QWIIC_SCL +#define CAM_SDA QWIIC_SDA + +// SPI bus +#define SPI_SCLK IO_39 +#define SPI_MOSI IO_44 +#define SPI_MISO IO_40 + #if defined(MBED_CONF_TARGET_STDIO_UART_TX) #define STDIO_UART_TX MBED_CONF_TARGET_STDIO_UART_TX #else diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/PinNames.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/PinNames.h index a9c6a872e3c..494bbbcf502 100644 --- a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/PinNames.h +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/PinNames.h @@ -38,69 +38,62 @@ extern "C" typedef enum { - // Digital naming - D0 = 0, - D1 = 1, - D2 = 2, - D3 = 3, - D4 = 4, - D5 = 5, - D6 = 6, - D7 = 7, - D8 = 8, - D9 = 9, - D10 = 10, - D11 = 11, - D12 = 12, - D13 = 13, - D14 = 14, - D15 = 15, - D16 = 16, - D17 = 17, - D18 = 18, - D19 = 19, - D20 = 20, - D21 = 21, - D22 = 22, - D23 = 23, - D24 = 24, - D25 = 25, - D26 = 26, - D27 = 27, - D28 = 28, - D29 = 29, - // D30 = NC - D31 = 31, - D32 = 32, - D33 = 33, - D34 = 34, - D35 = 35, - D36 = 36, - D37 = 37, - D38 = 38, - D39 = 39, - D40 = 40, - D41 = 41, - D42 = 42, - D43 = 43, - D44 = 44, - D45 = 45, + // Apollo3 I/O pins - CSP and BGA packages + IO_0 = 0, + IO_1 = 1, + IO_2 = 2, + IO_3 = 3, + IO_4 = 4, + IO_5 = 5, + IO_6 = 6, + IO_7 = 7, + IO_8 = 8, + IO_9 = 9, + IO_10 = 10, + IO_11 = 11, + IO_12 = 12, + IO_13 = 13, + IO_14 = 14, + IO_15 = 15, + IO_16 = 16, + IO_17 = 17, + IO_18 = 18, + IO_19 = 19, + IO_20 = 20, + IO_21 = 21, + IO_22 = 22, + IO_23 = 23, + IO_24 = 24, + IO_25 = 25, + IO_26 = 26, + IO_27 = 27, + IO_28 = 28, + IO_29 = 29, + IO_39 = 39, + IO_40 = 40, + IO_41 = 41, + IO_44 = 44, + IO_47 = 47, + IO_48 = 48, + IO_49 = 49, - // Analog naming - A11 = D11, - A12 = D12, - A13 = D13, - A16 = D16, - A29 = D29, - A31 = D31, - A32 = D32, - A33 = D33, - A34 = D34, - A35 = D35, + // Apollo3 I/O pins - BGA package only + IO_30 = 30, + IO_31 = 31, + IO_32 = 32, + IO_33 = 33, + IO_34 = 34, + IO_35 = 35, + IO_36 = 36, + IO_37 = 37, + IO_38 = 38, + IO_42 = 42, + IO_43 = 43, + IO_45 = 45, + IO_46 = 46, - LED1 = D1, - SERIAL_TX = 48, - SERIAL_RX = 49, + SERIAL_TX = IO_48, + SERIAL_RX = IO_49, CONSOLE_TX = SERIAL_TX, CONSOLE_RX = SERIAL_RX, From aa7a0d7e9869bcfc7a4a12343ccd767067634fc2 Mon Sep 17 00:00:00 2001 From: Jamie Smith Date: Thu, 3 Jul 2025 07:18:29 -0700 Subject: [PATCH 3/3] Update remaining PinNames.h files --- .../TARGET_SFE_ARTEMIS_NANO/PinNames.h | 129 +++++++++++----- .../TARGET_SFE_ARTEMIS_THING_PLUS/PinNames.h | 145 ++++++++++++------ 2 files changed, 186 insertions(+), 88 deletions(-) diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/PinNames.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/PinNames.h index 5674f77f442..b19f9a50604 100644 --- a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/PinNames.h +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/PinNames.h @@ -38,24 +38,78 @@ extern "C" typedef enum { + // Apollo3 I/O pins - CSP and BGA packages + IO_0 = 0, + IO_1 = 1, + IO_2 = 2, + IO_3 = 3, + IO_4 = 4, + IO_5 = 5, + IO_6 = 6, + IO_7 = 7, + IO_8 = 8, + IO_9 = 9, + IO_10 = 10, + IO_11 = 11, + IO_12 = 12, + IO_13 = 13, + IO_14 = 14, + IO_15 = 15, + IO_16 = 16, + IO_17 = 17, + IO_18 = 18, + IO_19 = 19, + IO_20 = 20, + IO_21 = 21, + IO_22 = 22, + IO_23 = 23, + IO_24 = 24, + IO_25 = 25, + IO_26 = 26, + IO_27 = 27, + IO_28 = 28, + IO_29 = 29, + IO_39 = 39, + IO_40 = 40, + IO_41 = 41, + IO_44 = 44, + IO_47 = 47, + IO_48 = 48, + IO_49 = 49, + + // Apollo3 I/O pins - BGA package only + IO_30 = 30, + IO_31 = 31, + IO_32 = 32, + IO_33 = 33, + IO_34 = 34, + IO_35 = 35, + IO_36 = 36, + IO_37 = 37, + IO_38 = 38, + IO_42 = 42, + IO_43 = 43, + IO_45 = 45, + IO_46 = 46, + // Digital naming - D0 = 13, - D1 = 33, - D2 = 11, - D3 = 29, - D4 = 18, - D5 = 31, - D6 = 43, - D7 = 42, - D8 = 38, - D9 = 39, - D10 = 40, - D11 = 5, - D12 = 7, - D13 = 6, - D14 = 35, - D15 = 32, - D16 = 12, + D0 = IO_13, + D1 = IO_33, + D2 = IO_11, + D3 = IO_29, + D4 = IO_18, + D5 = IO_31, + D6 = IO_43, + D7 = IO_42, + D8 = IO_38, + D9 = IO_39, + D10 = IO_40, + D11 = IO_5, + D12 = IO_7, + D13 = IO_6, + D14 = IO_35, + D15 = IO_32, + D16 = IO_12, // Analog naming A0 = D0, @@ -67,29 +121,6 @@ typedef enum A15 = D15, A16 = D16, - // LEDs - LED_BLUE = AM_BSP_GPIO_LED_BLUE, - - // mbed original LED naming - LED1 = AM_BSP_GPIO_LED0, - LED2 = D8, - - // I2C - I2C_SCL = AM_BSP_QWIIC_I2C_SCL_PIN, - I2C_SDA = AM_BSP_QWIIC_I2C_SDA_PIN, - - I2C1_SCL = AM_BSP_GPIO_IOM3_SCL, - I2C1_SDA = AM_BSP_GPIO_IOM3_SDA, - - // Qwiic - QWIIC_SCL = I2C_SCL, - QWIIC_SDA = I2C_SDA, - - // SPI - SPI_CLK = AM_BSP_PRIM_SPI_CLK_PIN, - SPI_SDO = AM_BSP_PRIM_SPI_SDO_PIN, - SPI_SDI = AM_BSP_PRIM_SPI_SDI_PIN, - // UART SERIAL_TX = AM_BSP_PRIM_UART_TX_PIN, SERIAL_RX = AM_BSP_PRIM_UART_RX_PIN, @@ -103,6 +134,24 @@ typedef enum NC = NC_VAL } PinName; +// LEDs +#define LED1 IO_19 // Blue LED + +// I2C bus +#define I2C_SCL IO_27 +#define I2C_SDA IO_25 + +#define I2C1_SCL IO_42 +#define I2C1_SDA IO_43 + +#define QWIIC_SCL I2C_SCL +#define QWIIC_SDA I2C_SDA + +// SPI bus +#define SPI_SCLK IO_5 +#define SPI_MOSI IO_7 +#define SPI_MISO IO_6 + #if defined(MBED_CONF_TARGET_STDIO_UART_TX) #define STDIO_UART_TX MBED_CONF_TARGET_STDIO_UART_TX #else diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/PinNames.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/PinNames.h index b8afe7de4e9..7aedda12847 100644 --- a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/PinNames.h +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/PinNames.h @@ -38,32 +38,86 @@ extern "C" typedef enum { + // Apollo3 I/O pins - CSP and BGA packages + IO_0 = 0, + IO_1 = 1, + IO_2 = 2, + IO_3 = 3, + IO_4 = 4, + IO_5 = 5, + IO_6 = 6, + IO_7 = 7, + IO_8 = 8, + IO_9 = 9, + IO_10 = 10, + IO_11 = 11, + IO_12 = 12, + IO_13 = 13, + IO_14 = 14, + IO_15 = 15, + IO_16 = 16, + IO_17 = 17, + IO_18 = 18, + IO_19 = 19, + IO_20 = 20, + IO_21 = 21, + IO_22 = 22, + IO_23 = 23, + IO_24 = 24, + IO_25 = 25, + IO_26 = 26, + IO_27 = 27, + IO_28 = 28, + IO_29 = 29, + IO_39 = 39, + IO_40 = 40, + IO_41 = 41, + IO_44 = 44, + IO_47 = 47, + IO_48 = 48, + IO_49 = 49, + + // Apollo3 I/O pins - BGA package only + IO_30 = 30, + IO_31 = 31, + IO_32 = 32, + IO_33 = 33, + IO_34 = 34, + IO_35 = 35, + IO_36 = 36, + IO_37 = 37, + IO_38 = 38, + IO_42 = 42, + IO_43 = 43, + IO_45 = 45, + IO_46 = 46, + // Digital naming - D0 = 25, - D1 = 24, - D2 = 44, - D3 = 35, - D4 = 4, - D5 = 22, - D6 = 23, - D7 = 27, - D8 = 28, - D9 = 32, - D10 = 14, - D11 = 7, - D12 = 6, - D13 = 5, - D14 = 40, - D15 = 39, - D16 = 43, - D17 = 42, - D18 = 26, - D19 = 33, - D20 = 13, - D21 = 11, - D22 = 29, - D23 = 12, - D24 = 31, + D0 = IO_25, + D1 = IO_24, + D2 = IO_44, + D3 = IO_35, + D4 = IO_4, + D5 = IO_22, + D6 = IO_23, + D7 = IO_27, + D8 = IO_28, + D9 = IO_32, + D10 = IO_14, + D11 = IO_7, + D12 = IO_6, + D13 = IO_5, + D14 = IO_40, + D15 = IO_39, + D16 = IO_43, + D17 = IO_42, + D18 = IO_26, + D19 = IO_33, + D20 = IO_13, + D21 = IO_11, + D22 = IO_29, + D23 = IO_12, + D24 = IO_31, // Analog naming A0 = D19, @@ -74,29 +128,6 @@ typedef enum A5 = D24, A6 = D3, - //BUTTONs - SW1 = AM_BSP_GPIO_BUTTON0, - - // LEDs - LED_BLUE = AM_BSP_GPIO_LED_BLUE, - - // mbed original LED naming - LED1 = AM_BSP_GPIO_LED0, - LED2 = D2, - - // I2C - I2C_SCL = AM_BSP_QWIIC_I2C_SCL_PIN, - I2C_SDA = AM_BSP_QWIIC_I2C_SDA_PIN, - - // Qwiic - QWIIC_SCL = I2C_SCL, - QWIIC_SDA = I2C_SDA, - - // SPI - SPI_CLK = AM_BSP_PRIM_SPI_CLK_PIN, - SPI_SDO = AM_BSP_PRIM_SPI_SDO_PIN, - SPI_SDI = AM_BSP_PRIM_SPI_SDI_PIN, - // UART SERIAL_TX = AM_BSP_PRIM_UART_TX_PIN, SERIAL_RX = AM_BSP_PRIM_UART_RX_PIN, @@ -110,6 +141,24 @@ typedef enum NC = NC_VAL } PinName; +// LEDs +#define LED1 IO_26 // Blue LED + +// Buttons +#define BUTTON1 IO_14 + +// I2C bus +#define I2C_SCL IO_39 +#define I2C_SDA IO_40 + +#define QWIIC_SCL I2C_SCL +#define QWIIC_SDA I2C_SDA + +// SPI bus +#define SPI_SCLK IO_5 +#define SPI_MOSI IO_7 +#define SPI_MISO IO_6 + #if defined(MBED_CONF_TARGET_STDIO_UART_TX) #define STDIO_UART_TX MBED_CONF_TARGET_STDIO_UART_TX #else