MPAE-18704 updated README based on Marketing and Tech Writers edits

CoffeeConsumer · CoffeeConsumer · commit e3332f6b6f98 · 2024-12-12T08:17:57.000-07:00
diff --git a/README.md b/README.md
@@ -6,8 +6,8 @@
    </picture>
 </a>
 
-# Implementing a hardware-based state machine for communicating with DHT22 sensor using PIC18F46Q24 
-This code example demonstrates how the Signal Routing (SR) Port can be used together with other Core Independent Peripherals (CIP)s on PIC® microcontrollers to implement a state machine for communicating with a DHT22 sensor with minimal software intervention.
+# Implementing a Hardware-based State Machine for Communicating with DHT22 Sensor using PIC18F46Q24 
+The Signal Routing (SR) Port, is a peripheral that allows for flexible connections of other PIC® microcontroller peripherals without the need for dedicating Input/Output (I/O) pins and routing wires. The SR Port can be read and written from software just like a normal I/O port, and each pin in the port can optionally be configured to be clocked, allowing each pin to act as a flip-flop. The unique features of the SR Port make it possible to build state machines that can run without software intervention, which can greatly enhance the performance of the system. This code example demonstrates how the SR Port can be used together with other Core Independent Peripherals (CIP)s on PIC® microcontrollers to implement a state machine for communicating with a DHT22 sensor with minimal software intervention.
 
 ## Related Documentation
 
@@ -33,23 +33,23 @@ This code example demonstrates how the Signal Routing (SR) Port can be used toge
 
 Finite State Machines (FSM)s are an important concept in the design of digital systems. A traditional FSM consists of three main components:
 
-   - Memory. The memory of the state machine hold the current state of the system
-   - Next State Logic. The Next State Logic dictates how the system will transistion from one state to the next based on the current state and the input.
-   - Output Logic. The output logic controls the outputs of the system based on the current state in the case of a Moore Machine, or a combination of inputs and the current state, in the case of a Mealy Machine.
+   - Memory: The memory of the state machine hold the current state of the system
+   - Next State Logic: The Next State Logic dictates how the system will transistion from one state to the next based on the current state and the input.
+   - Output Logic: The output logic controls the outputs of the system based on the current state in the case of a Moore Machine, or a combination of inputs and the current state, in the case of a Mealy Machine.
    
-When building embedded systems, FSMs are typically implemented in software. Using the SR PORT, Configurable Logic Cells (CLC)s, and other peripherals present on PIC microcontrollers, it is possible to build functional state machines that can operate with little or no CPU intervention. Implementing state machines this way frees up the CPU to perfrom other tasks, which can greatly improve the peformance of a system. The Figure below illustrates how state machines can be implemented using the SR PORT and CLCs:
+When building embedded systems, FSMs are typically implemented in software. Using the SR PORT, Configurable Logic Cells (CLC)s, and other peripherals present on PIC microcontrollers, it is possible to build functional state machines that can operate with little or no CPU intervention. Implementing state machines this way frees up the CPU to perfrom other tasks, which can greatly improve the peformance of a system. The figure below illustrates how state machines can be implemented using the SR PORT and CLCs:
 <br><img src="images/Moore State Machine.png">
 <br><img src="images/Mealy State Machine.png">
 
 
 ## DHT22 Sensor
 
 The DHT22 Sensor is a temperature/humidity sensor that uses a custom single wire protocol for transmitting data. The sensor transmits 40 bits of data: two bytes for the temperature data, two bytes for the humidity data, and one checksum byte. Getting data from the sensor consists of three steps:
-1. The controller pulls the data line low for 20 milliseconds to intiate communication with the sensor and then releases the line
-2. After 20 microseconds, the sensor pulls the data line low for 50 microseconds and then releases the data line
-3. After another 50 microseconds, the sensor starts transmitting data
+1. The controller pulls the data line low for 20 milliseconds to intiate communication with the sensor and then releases the line.
+2. After 20 microseconds, the sensor pulls the data line low for 50 microseconds and then releases the data line.
+3. After another 50 microseconds, the sensor starts transmitting data.
 <br>
-The sensor transmits each bit by pulling the data line low for 50 microseconds and then releasing the line. To transmit a `'0'` the sensor releases the line for 28 microseconds before transmitting the next bit. To transmit a `'1'`, the sensor releases the line for 70 microseconds before transmitting the next bit. The waveform below illustrates the transmission process.
+The sensor transmits each bit by pulling the data line low for 50 microseconds and then releasing the line. To transmit a `'0'` the sensor releases the line for 28 microseconds before transmitting the next bit. To transmit a `'1'`, the sensor releases the line for 70 microseconds before transmitting the next bit. The waveform below illustrates the transmission process:
 
 <br><img src="images/DHT22_Signal.png">  
 
@@ -61,7 +61,7 @@ Using the SRPORT and CIPs, getting data from the DHT22 sensor can be done entire
 
 |  State   |                  Output                      |  Binary Encoding   | 
 |:--------:|:--------------------------------------------:|:------------------:|
-|  IDLE    | Data line is released. No transaction on bus |       `000`        |
+|  IDLE    | Data line is released. No transaction on bus.|       `000`        |
 |  START   | Data line is pulled low by microcontroller   |       `001`        |
 |  W1      | Data line = 1                                |       `010`        |
 |  W2      | Data line = 0                                |       `011`        |
@@ -72,15 +72,15 @@ The state machine will have three inputs:
 
 |  Input Label  |  Source           |               Description                        |
 |:-------------:|:-----------------:|:------------------------------------------------:|
-|      U        | Universal Timer B | Generates a 20ms low pulse to start transmission |
+|      U        | Universal Timer B | Generates a 20 ms low pulse to start transmission|
 |      D        | I/O PORTD3        | The physical bi-directional data line            |
 |      F        | Universal Timer A | Signals the end of the 40 bit transmission state |
 
 
 The transitions between each state can be described using a state transistion diagram:
 <br><img src="images/DHT22_State_Diagram.png"> 
 
-To start the transmission, TU16B is used in one-shot mode to generate a 20ms low pulse on the
+To start the transmission, TU16B is used in one-shot mode to generate a 20 ms low pulse on the
 DHT22 data line. Once the line is released, the state machine will look for a pattern of high, low, high, low to detect when the DHT22 will begin to transmit data. Once the state machine enters the RX state, the SPI is used in conjunction with Timer 2 and one CLC to read each bit. The CLC is used to produce a version of the DHT22 signal without the start and wait sections. Using the SR PORT, this signal can then be routed internally to the data line of the SPI. Timer 2 can use this signal to produce a clock signal for the SPI that will allow the SPI to clock in either a `‘1’` or `‘0’`. Universal Timer A is used to count the number of bits transmitted by the DHT22 and generate the F signal once 40 bits have been detected. A timing diagram illustrating a complete transmission process is shown below:
 <br><img src="images/DHT22_Timing_Diagram.png">
 
@@ -91,14 +91,14 @@ Once the state transitions have been determined, a Sum-of-Products (SOP) Boolean
 <br><img src="images/DHT22_S1_SOP.png">
 <br><img src="images/DHT22_S2_SOP.png">
 
-Since S<sub>2</sub> and S<sub>0</sub> each have a common term, this can be implemented using one CLC to reduce teh number of CLCs needed. Because each CLC has a 4-input AND configuration, it will be easier to implement the equations for S<sub>1</sub>, CLC5, and CLC6 if they are written as Product-of-Sums (POS) equations rather than SOP equations.
+Since S<sub>2</sub> and S<sub>0</sub> each have a common term, this can be implemented using one CLC to reduce the number of CLCs needed. Because each CLC has a 4-input AND configuration, it will be easier to implement the equations for S<sub>1</sub>, CLC5, and CLC6 if they are written as Product-of-Sums (POS) equations rather than SOP equations.
 <br><img src="images/DHT22_S1_POS.png">
 <br><img src="images/DHT22_CLC5_POS.png">
 <br><img src="images/DHT22_CLC7_POS.png">
 
 ## Implementation
 
-Once the state machine logic has been defined, the system can be implemented using MPLAB Melody Code Configurator. Melody is tool built in to MPLAB X that makes it easy generate code for any of the on-chip peripherals present on PIC microcontrollers. Using Melody it is easy to implement the hardware state machine with just a few clicks. The following images show the configuration of the CLCs and SR PORT
+Once the state machine logic has been defined, the system can be implemented using MPLAB Melody Code Configurator. Melody is a tool built in to MPLAB X that makes it easy generate code for any of the on-chip peripherals present on PIC microcontrollers. Using Melody it is easy to implement the hardware state machine with just a few clicks. The following images show the configuration of the CLCs and SR PORT
 <br><br>
 **CLC1**
 <br><img src="images/CLC1.png"><br>
@@ -136,5 +136,5 @@ Once the peripherals are configured and code has been generated, all that is nee
 <br><img src="images/terminal_output.png"><br>
 
 ## Summary
- The SR PORT allows for advanced interconnectivity between CIPs on PIC microcontrollers. It also has the ability to individually configure each bit as a flip-flop, which enable allows the SR PORT to act as a memory element in a hardware state machine. Using the SR PORT in combination with the CLCs makes it possible to build core-independent state machinces that can offload tasks from the CPU and greatly increase system performance. This code example shows how the SR PORT can be used to seamlessly connect the on-chip peripherals of PIC microcontrollers and use the flip-flop feature of the SR PORT to implement a hardware state machine that is useful in a real-world scenario.
+ The SR PORT allows for advanced interconnectivity between CIPs on PIC microcontrollers. It also has the ability to individually configure each bit as a flip-flop, which when enabled allows the SR PORT to act as a memory element in a hardware state machine. Using the SR PORT in combination with the CLCs makes it possible to build core-independent state machinces that can offload tasks from the CPU and greatly increase system performance. This code example shows how the SR PORT can be used to seamlessly connect the on-chip peripherals of PIC microcontrollers and use the flip-flop feature of the SR PORT to implement a hardware state machine that is useful in a real-world scenario.
 
