update to v1.16.0

mshr-h · mshr-h · commit 2677b56e849d · 2025-01-23T11:22:36.000+09:00
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -4,7 +4,7 @@ All notable changes to this project will be documented in this file.
 
 The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/)
 
-## [1.15.6] - 2025-01-22
+## [1.16.0] - 2025-01-23
 
 ### Added
 
diff --git a/package-lock.json b/package-lock.json
diff --git a/package.json b/package.json
@@ -2,7 +2,7 @@
   "name": "veriloghdl",
   "displayName": "Verilog-HDL/SystemVerilog/Bluespec SystemVerilog",
   "description": "Verilog-HDL/SystemVerilog/Bluespec SystemVerilog support for VS Code",
-  "version": "1.15.5",
+  "version": "1.16.0",
   "publisher": "mshr-h",
   "homepage": "https://github.com/mshr-h/vscode-verilog-hdl-support",
   "repository": {
