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Fix implication operator highlight (#506)
* fix syntax highlighting for implication operator * add language example for implication operator
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3 files changed

+27
-12
lines changed

3 files changed

+27
-12
lines changed
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@@ -0,0 +1,15 @@
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module test;
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wire a, b;
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property p;
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@(posedge clk) a |-> b;
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endproperty
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a: assert property(p);
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property p;
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@(posedge clk) a |=> b;
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endproperty
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a: assert property(p);
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endmodule

syntaxes/systemverilog.tmLanguage.json

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@@ -878,6 +878,14 @@
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},
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"operators": {
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"patterns": [
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{
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"match": "\\b(?:dist|inside|with|intersect|and|or|throughout|within|first_match)\\b|:=|:/|\\|->|\\|=>|->>|\\*>|#-#|#=#|&&&",
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"name": "keyword.operator.logical.systemverilog"
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},
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{
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"match": "@|##|#|->|<->",
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"name": "keyword.operator.channel.systemverilog"
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},
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{
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"match": "\\+=|-=|/=|\\*=|%=|&=|\\|=|\\^=|>>>=|>>=|<<<=|<<=|<=|=",
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"name": "keyword.operator.assignment.systemverilog"
@@ -909,14 +917,6 @@
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{
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"match": "<=|<|>=|>|==\\?|!=\\?|===|!==|==|!=",
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"name": "keyword.operator.comparison.systemverilog"
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},
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{
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"match": "@|##|#|->|<->",
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"name": "keyword.operator.channel.systemverilog"
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},
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{
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"match": "\\b(?:dist|inside|with|intersect|and|or|throughout|within|first_match)\\b|:=|:/|\\|->|\\|=>|->>|\\*>|#-#|#=#|&&&",
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"name": "keyword.operator.logical.systemverilog"
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}
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]
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},

syntaxes/systemverilog.tmLanguage.yaml

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@@ -472,6 +472,10 @@ repository:
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name: keyword.operator.quantifier.regexp
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operators:
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patterns:
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- match: \b(?:dist|inside|with|intersect|and|or|throughout|within|first_match)\b|:=|:/|\|->|\|=>|->>|\*>|#-#|#=#|&&&
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name: keyword.operator.logical.systemverilog
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- match: '@|##|#|->|<->'
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name: keyword.operator.channel.systemverilog
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- match: \+=|-=|/=|\*=|%=|&=|\|=|\^=|>>>=|>>=|<<<=|<<=|<=|=
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name: keyword.operator.assignment.systemverilog
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# - match: :|\?
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name: keyword.operator.bitwise.systemverilog
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- match: <=|<|>=|>|==\?|!=\?|===|!==|==|!=
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name: keyword.operator.comparison.systemverilog
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- match: '@|##|#|->|<->'
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name: keyword.operator.channel.systemverilog
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- match: \b(?:dist|inside|with|intersect|and|or|throughout|within|first_match)\b|:=|:/|\|->|\|=>|->>|\*>|#-#|#=#|&&&
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name: keyword.operator.logical.systemverilog
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comments:
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patterns:
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- begin: /\*

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