update to v1.15.0

Author: mshr-h

CHANGELOG.md

@@ -4,11 +4,16 @@ All notable changes to this project will be documented in this file.
 
 The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/)\
 
-## [Unreleased]
+## [1.15.0] - 2024-08-26
 
 ## Added
+
 - Pass arguments to lsp [#446][https://github.com/mshr-h/vscode-verilog-hdl-support/issues/446]
 
+## Fixed
+
+- Fix #479 by add parameters back into Module instantiation [#496](https://github.com/mshr-h/vscode-verilog-hdl-support/pull/496)
+
 ## [1.14.3] - 2024-07-30
 
 ## Added

package-lock.json

@@ -2,7 +2,7 @@
   "name": "veriloghdl",
   "displayName": "Verilog-HDL/SystemVerilog/Bluespec SystemVerilog",
   "description": "Verilog-HDL/SystemVerilog/Bluespec SystemVerilog support for VS Code",
-  "version": "1.14.3",
+  "version": "1.15.0",
   "publisher": "mshr-h",
   "homepage": "https://github.com/mshr-h/vscode-verilog-hdl-support",
   "repository": {