[BUG] syntax highlighting doesn't properly parse dollar signs, $, in identifiers

[bsferrazza]

Describe the bug
Most people seem unware of this, but $ are legal characters in Verilog (as long as they are not the first character) for identifiers (ports, nets, parameters, modules, instances, etc). This has been the case since the inception of the language over 30 years ago. They are nice to use as another way to delimit text besides an underscore.

Environment (please complete the following information):

• OS: Applies to All
• VS Code version [e.g. 1.0.0] All versions
• Extension version [e.g. 1.0.1] All versions
• color themes, lint tools, etc. N/A

Steps to reproduce
Simply use identifiers with $

assign r$some_reg$d = w$some_net$b;

Expected behavior
I expect it to properly parse $ in identifiers and keep consistent colors based on the identifier type and context.

Actual behavior
The coloring is inconsistent and disjointed with colors changing mid-identifier.