[error] No output from ctags

[dominiksalvet]

Hello,
when I switch between systemverilog files, in VSCode output terminal in Verilog tab, the following error appears:

2025-07-10 19:48:36.650 [info] [VerilogDocumentSymbolProvider] [VerilogSymbol] Symbols Requested: file://<path>.sv
2025-07-10 19:48:36.650 [info] indexing "<path>.sv"
2025-07-10 19:48:36.650 [info] executing ctags
2025-07-10 19:48:36.650 [info] building symbols
2025-07-10 19:48:36.650 [error] No output from ctags
2025-07-10 19:48:36.650 [info] [VerilogDocumentSymbolProvider] 0 top-level symbols returned

Do you have any idea why? Also tried to make run some language servers but was unable to make port name completions and this kind of stuff work. Does it relate? These errors appear even if no LS is enabled.