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Pragma support (#15)
* pragma support in progress * update code * code cleaning * code cleaning * adding pragmas at various places in code * cleaning collect in attributes testing * testing more pragmas * remove some paths from codecov * Fix path * Fix path * Fix path again * license and path * Try again * last attempt ? * new test * another attempt * fix path * fix lcov * fix path * start cleaning * more cleaning * save current state * Adding getType to ConstantExpression
1 parent d10d53e commit e24707c

18 files changed

+283
-72
lines changed

‎.github/workflows/coverage.yml

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -48,16 +48,15 @@ jobs:
4848
run: |
4949
lcov --directory . --capture --output-file coverage.info
5050
lcov --remove coverage.info --output-file coverage.info '/usr/*' '*/naja-verilog/test/*' '*/naja-verilog/thirdparty/*'
51+
lcov --list coverage.info
5152
- name: Upload coverage to Codecov
5253
uses: codecov/codecov-action@v4
5354
env:
5455
CODECOV_TOKEN: ${{ secrets.CODECOV_TOKEN }}
5556
with:
56-
directory: ${{github.workspace}}/build
57-
#env_vars: OS,PYTHON
5857
fail_ci_if_error: true
59-
files: coverage.info
58+
file: ${{github.workspace}}/build/coverage.info
59+
disable_search: true
6060
flags: unittests
6161
name: codecov-umbrella
62-
#path_to_write_report: ./coverage/codecov_report.txt
6362
verbose: true

‎.reuse/dep5

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@ Upstream-Name: naja-verilog
33
Upstream-Contact: Christophe Alexandre <christophe.alex@gmail.com>
44
Source: https://github.com/najaeda/naja-verilog
55

6-
Files: .github/workflows/* .gitmodules .gitignore
6+
Files: .github/workflows/* .gitmodules .gitignore .codecov.yml
77
Copyright: 2023 The Naja verilog Authors.
88
License: Apache-2.0
99

‎src/NajaVerilogSnippet.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@ class VerilogConstructorExample: public naja::verilog::VerilogConstructor {
4747
}
4848
virtual void addDefParameterAssignment(
4949
const naja::verilog::Identifiers& hierarchicalParameter,
50-
const naja::verilog::Expression& expression) override {
50+
const naja::verilog::ConstantExpression& expression) override {
5151
std::ostringstream oss;
5252
for (size_t i = 0; i < hierarchicalParameter.size(); i++) {
5353
oss << hierarchicalParameter[i].getString();

‎src/VerilogConstructor.h

Lines changed: 13 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -50,23 +50,26 @@ class VerilogConstructor {
5050
}
5151

5252
//LCOV_EXCL_START
53-
virtual void startModule(const naja::verilog::Identifier& id) {}
53+
virtual void startModule(const Identifier& id) {}
5454
//Simple Port declaration (only name), no range, no direction in module interface
55-
virtual void moduleInterfaceSimplePort(const naja::verilog::Identifier& port) {}
55+
virtual void moduleInterfaceSimplePort(const Identifier& port) {}
5656
//Complete Port declaration in module interface
5757
virtual void moduleInterfaceCompletePort(const Port& port) {}
5858
virtual void moduleImplementationPort(const Port& port) {}
5959
virtual void addNet(const Net& net) {}
6060
virtual void addAssign(const RangeIdentifiers& identifiers, const Expression& expression) {}
61-
virtual void startInstantiation(const naja::verilog::Identifier& model) {}
62-
virtual void addInstance(const naja::verilog::Identifier& instance) {}
63-
virtual void addInstanceConnection(const naja::verilog::Identifier& port, const Expression& expression) {}
61+
virtual void startInstantiation(const Identifier& model) {}
62+
virtual void addInstance(const Identifier& instance) {}
63+
virtual void addInstanceConnection(const Identifier& port, const Expression& expression) {}
6464
virtual void addOrderedInstanceConnection(size_t portIndex, const Expression& expression) {}
6565
virtual void endInstantiation() {}
66-
virtual void addParameterAssignment(const naja::verilog::Identifier& parameter, const Expression& expression) {}
66+
virtual void addParameterAssignment(const Identifier& parameter, const Expression& expression) {}
6767
virtual void addDefParameterAssignment(
68-
const naja::verilog::Identifiers& hierarchicalParameter,
69-
const naja::verilog::Expression& expression) {}
68+
const Identifiers& hierarchicalParameter,
69+
const ConstantExpression& expression) {}
70+
virtual void addAttribute(
71+
const Identifier& attributeName,
72+
const ConstantExpression& expression) {}
7073
virtual void endModule() {}
7174
//LCOV_EXCL_STOP
7275
private:
@@ -83,9 +86,9 @@ class VerilogConstructor {
8386
ModuleInterfaceTypeEnum typeEnum_;
8487
};
8588
void internalParse(std::istream& stream);
86-
void internalStartModule(const naja::verilog::Identifier& id);
89+
void internalStartModule(const Identifier& id);
8790
void internalEndModule();
88-
void internalModuleInterfaceSimplePort(const naja::verilog::Identifier& id);
91+
void internalModuleInterfaceSimplePort(const Identifier& id);
8992
void internalModuleInterfaceCompletePort(const Port& port);
9093
void internalModuleImplementationPort(const Port& port);
9194

‎src/VerilogParser.yy

Lines changed: 43 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -159,17 +159,19 @@ static naja::verilog::Number generateNumber(
159159
%type<naja::verilog::Identifier> port_identifier;
160160

161161
%type<naja::verilog::Number> number;
162-
%type<naja::verilog::Expression> constant_mintypmax_expression;
162+
%type<naja::verilog::ConstantExpression> constant_primary;
163+
%type<naja::verilog::ConstantExpression> constant_expression;
164+
%type<naja::verilog::ConstantExpression> constant_mintypmax_expression;
163165
%type<std::string> unary_operator;
164166
%type<naja::verilog::Expression> primary;
165-
%type<naja::verilog::Expression> constant_primary;
166-
%type<naja::verilog::Expression> constant_expression;
167167
%type<naja::verilog::Expression> expression;
168168
%type<naja::verilog::Expression> expression.opt;
169169
%type<naja::verilog::Expression> mintypmax_expression;
170170
%type<naja::verilog::Expression> mintypmax_expression.opt;
171171
%type<naja::verilog::Expression::Expressions> concatenation;
172172
%type<naja::verilog::Expression::Expressions> list_of_expressions;
173+
%type<naja::verilog::ConstantExpression> attr_spec_value;
174+
%type<naja::verilog::Attribute> attr_spec;
173175

174176
%locations
175177
%start source_text
@@ -212,7 +214,7 @@ constant_expression: constant_primary {
212214
}
213215
| unary_operator constant_primary {
214216
auto expression = $2;
215-
if (expression.value_.index() == naja::verilog::Expression::NUMBER) {
217+
if (expression.value_.index() == naja::verilog::ConstantExpression::NUMBER) {
216218
auto number = std::get<naja::verilog::Number>(expression.value_);
217219
if ($1 == "-") { number.sign_ = false; }
218220
$$.valid_ = true;
@@ -223,8 +225,8 @@ constant_expression: constant_primary {
223225
}
224226

225227
range: '[' constant_expression ':' constant_expression ']' {
226-
if ($2.value_.index() == naja::verilog::Expression::NUMBER and
227-
$4.value_.index() == naja::verilog::Expression::NUMBER) {
228+
if ($2.value_.index() == naja::verilog::ConstantExpression::NUMBER and
229+
$4.value_.index() == naja::verilog::ConstantExpression::NUMBER) {
228230
auto number1 = std::get<naja::verilog::Number>($2.value_);
229231
auto number2 = std::get<naja::verilog::Number>($4.value_);
230232
$$ = Range(number1.getInt(), number2.getInt());
@@ -235,14 +237,14 @@ range: '[' constant_expression ':' constant_expression ']' {
235237

236238
range.opt: %empty { $$.valid_ = false; } | range { $$ = $1; }
237239

238-
port_declaration: port_type_io range.opt identifier {
239-
$$ = Port($3, $1, $2);
240+
port_declaration: list_of_attribute_instance.opt port_type_io range.opt identifier {
241+
$$ = Port($4, $2, $3);
240242
}
241243

242-
internal_ports_declaration: port_type_io range.opt list_of_identifiers {
244+
internal_ports_declaration: list_of_attribute_instance.opt port_type_io range.opt list_of_identifiers {
243245
constructor->setCurrentLocation(@$.begin.line, @$.begin.column);
244-
for (auto portIdentifier: $3) {
245-
constructor->internalModuleImplementationPort(Port(portIdentifier, $1, $2));
246+
for (auto portIdentifier: $4) {
247+
constructor->internalModuleImplementationPort(Port(portIdentifier, $2, $3));
246248
}
247249
}
248250

@@ -295,10 +297,10 @@ list_of_net_assignments: net_assignment | list_of_net_assignments ',' net_assign
295297
continuous_assign: ASSIGN_KW list_of_net_assignments ';'
296298

297299
module_or_generate_item:
298-
module_or_generate_item_declaration
299-
| module_instantiation
300-
| parameter_override
301-
| continuous_assign
300+
list_of_attribute_instance.opt module_or_generate_item_declaration
301+
| list_of_attribute_instance.opt module_instantiation
302+
| list_of_attribute_instance.opt parameter_override
303+
| list_of_attribute_instance.opt continuous_assign
302304
;
303305

304306
module_or_generate_item_declaration: net_declaration;
@@ -357,7 +359,7 @@ hierarchical_identifier
357359
//only numeric values (one bit) [4] or [4:5] are supported
358360
constant_range_expression.opt: %empty { $$.valid_ = false; }
359361
| '[' constant_expression ']' {
360-
if ($2.value_.index() == naja::verilog::Expression::NUMBER) {
362+
if ($2.value_.index() == naja::verilog::ConstantExpression::NUMBER) {
361363
auto number = std::get<naja::verilog::Number>($2.value_);
362364
$$ = Range(number.getInt());
363365
} else {
@@ -470,14 +472,37 @@ list_of_module_args: module_arg | list_of_module_args ',' module_arg;
470472

471473
list_of_module_args.opt: %empty | '(' ')' | '(' list_of_module_args ')';
472474

473-
module_declaration: MODULE_KW module_identifier {
475+
module_declaration: list_of_attribute_instance.opt {
476+
} MODULE_KW module_identifier {
474477
constructor->setCurrentLocation(@$.begin.line, @$.begin.column);
475-
constructor->internalStartModule(std::move($2));
478+
constructor->internalStartModule(std::move($4));
476479
} list_of_module_args.opt ';' list_of_module_items.opt ENDMODULE_KW {
477480
constructor->setCurrentLocation(@$.begin.line, @$.begin.column);
478481
constructor->internalEndModule();
479482
}
480483

484+
/* 3.8 */
485+
attr_spec_value: %empty {
486+
$$.valid_ = false;
487+
}
488+
| '=' constant_expression {
489+
$$ = $2;
490+
}
491+
492+
attr_spec: identifier attr_spec_value {
493+
constructor->setCurrentLocation(@$.begin.line, @$.begin.column);
494+
constructor->addAttribute($1, $2);
495+
}
496+
497+
list_of_attr_spec: attr_spec | list_of_attr_spec ',' attr_spec;
498+
499+
//A.9.1
500+
attribute_instance: '(' '*' list_of_attr_spec '*' ')';
501+
502+
list_of_attribute_instance: attribute_instance | list_of_attribute_instance attribute_instance;
503+
504+
list_of_attribute_instance.opt: %empty | list_of_attribute_instance;
505+
481506
%%
482507

483508
void naja::verilog::VerilogParser::error(

‎src/VerilogScanner.ll

Lines changed: 1 addition & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,6 @@ using token = naja::verilog::VerilogParser::token;
4242
%option c++
4343

4444
%x in_comment
45-
%x in_attribute
4645
%x based_const
4746

4847
/* Predefined rules */
@@ -52,9 +51,6 @@ COMMENT_BEGIN "/*"
5251
COMMENT_END "*/"
5352
COMMENT_LINE "//".*\n
5453
55-
ATTRIBUTE_BEGIN "(*"
56-
ATTRIBUTE_END "*)"
57-
5854
IDENTIFIER [_a-zA-Z][$_a-zA-Z0-9]*
5955
UNSIGNED_NUMBER [0-9][0-9_]*
6056
STRING \"[^\"]*\"
@@ -92,20 +88,7 @@ ESCAPED_IDENTIFIER \\[\\^!"#$%&',()*+\-.a-zA-Z0-9/{|}~[\]_:;<=>?@]+[\n\t\f ]
9288
<in_comment>. { /* ignore characters in comment */ }
9389
<in_comment>{COMMENT_END} { BEGIN(INITIAL); }
9490
95-
{ATTRIBUTE_BEGIN} { BEGIN(in_attribute); }
96-
<in_attribute><<EOF>> {
97-
BEGIN(INITIAL);
98-
std::ostringstream reason;
99-
reason << "Unclosed attribute at line "
100-
<< loc->end.line << " col " << loc->end.column;
101-
throw VerilogException(reason.str());
102-
}
103-
104-
<in_attribute>{NEWLINE} { loc->lines(); }
105-
<in_attribute>. { /* ignore characters in comment */ }
106-
<in_attribute>{ATTRIBUTE_END} { BEGIN(INITIAL); }
107-
108-
"."|","|";"|"("|")"|"#"|"["|"]"|":"|"{"|"}"|"=" {
91+
"."|","|";"|"("|")"|"*"|"#"|"["|"]"|":"|"{"|"}"|"=" {
10992
return yytext[0];
11093
}
11194

‎src/VerilogTypes.cpp

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -266,4 +266,33 @@ std::string Expression::getDescription() const {
266266
}
267267
//LCOV_EXCL_STOP
268268

269+
//LCOV_EXCL_START
270+
std::string ConstantExpression::getString() const {
271+
std::ostringstream stream;
272+
switch (value_.index()) {
273+
case Type::NUMBER:
274+
return std::get<Type::NUMBER>(value_).getString();
275+
case Type::STRING:
276+
return std::get<Type::STRING>(value_);
277+
}
278+
return std::string();
279+
}
280+
//LCOV_EXCL_STOP
281+
282+
//LCOV_EXCL_START
283+
std::string ConstantExpression::getDescription() const {
284+
std::ostringstream stream;
285+
stream << "Expression: (valid: " << valid_ << ") ";
286+
switch (value_.index()) {
287+
case Type::NUMBER:
288+
stream << std::get<Type::NUMBER>(value_).getDescription();
289+
break;
290+
case Type::STRING:
291+
stream << std::get<Type::STRING>(value_);
292+
break;
293+
}
294+
return stream.str();
295+
}
296+
//LCOV_EXCL_STOP
297+
269298
}} // namespace verilog // namespace naja

‎src/VerilogTypes.h

Lines changed: 31 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -228,13 +228,42 @@ struct Expression {
228228
enum Type { RANGEIDENTIFIER=0, NUMBER=1, STRING=2, CONCATENATION=3 };
229229
using Value = std::variant<RangeIdentifier, Number, std::string, Concatenation>;
230230

231-
bool valid_ {false};
231+
bool valid_ { false };
232232
//If valid_ is true and supported_ is false, then this expression construction
233233
//is not currently supported.
234-
bool supported_ {true};
234+
bool supported_ { true };
235235
Value value_ {};
236236
};
237237

238+
struct ConstantExpression {
239+
ConstantExpression() = default;
240+
ConstantExpression(const ConstantExpression&) = default;
241+
242+
enum Type { NUMBER=0, STRING=1 };
243+
using Value = std::variant<Number, std::string>;
244+
245+
Type getType() const { return Type(value_.index()); }
246+
std::string getString() const;
247+
std::string getDescription() const;
248+
249+
bool valid_ { false };
250+
Value value_ {};
251+
};
252+
253+
struct Attribute {
254+
Attribute() = default;
255+
Attribute(const Attribute&) = default;
256+
Attribute(const naja::verilog::Identifier& name, const ConstantExpression& expression):
257+
name_(name),
258+
expression_(expression)
259+
{}
260+
std::string getString() const;
261+
std::string getDescription() const;
262+
263+
naja::verilog::Identifier name_ {};
264+
ConstantExpression expression_ {};
265+
};
266+
238267
}} // namespace verilog // namespace naja
239268

240269
#endif /* __VERILOG_TYPES_H_ */

‎test/CMakeLists.txt

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,8 @@ set(tests
1818
NajaVerilogTest11.cpp
1919
NajaVerilogTest12.cpp
2020
NajaVerilogTest13.cpp
21+
NajaVerilogTest14.cpp
22+
NajaVerilogTest15.cpp
2123
NajaVerilogTestMultipleFiles.cpp
2224
NajaVerilogTestErrors.cpp
2325
)

‎test/NajaVerilogTest12.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,7 @@ TEST(NajaVerilogTest12, test) {
6868
EXPECT_EQ("INIT", def0Path[1].name_);
6969
EXPECT_FALSE(def0Path[1].escaped_);
7070
EXPECT_EQ("2'h1", def0Value.getString());
71-
EXPECT_EQ(Expression::Type::NUMBER ,def0Value.value_.index());
71+
EXPECT_EQ(ConstantExpression::Type::NUMBER ,def0Value.value_.index());
7272

7373
auto def1Path = test->defParameterAssignments_[1].first;
7474
auto def1Value = test->defParameterAssignments_[1].second;
@@ -77,7 +77,7 @@ TEST(NajaVerilogTest12, test) {
7777
EXPECT_FALSE(def1Path[0].escaped_);
7878
EXPECT_EQ("RAMINDEX", def1Path[1].name_);
7979
EXPECT_FALSE(def1Path[1].escaped_);
80-
EXPECT_EQ(Expression::Type::STRING ,def1Value.value_.index());
80+
EXPECT_EQ(ConstantExpression::Type::STRING ,def1Value.value_.index());
8181
EXPECT_EQ("mem_regfile[7:0]%32%8%SPEED%0%0%MICRO_RAM", def1Value.getString());
8282

8383
auto def2Path = test->defParameterAssignments_[2].first;
@@ -87,6 +87,6 @@ TEST(NajaVerilogTest12, test) {
8787
EXPECT_TRUE(def2Path[0].escaped_);
8888
EXPECT_EQ("INIT", def2Path[1].name_);
8989
EXPECT_FALSE(def2Path[1].escaped_);
90-
EXPECT_EQ(Expression::Type::NUMBER ,def2Value.value_.index());
90+
EXPECT_EQ(ConstantExpression::Type::NUMBER ,def2Value.value_.index());
9191
EXPECT_EQ("2'h2", def2Value.getString());
9292
}

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