Fix Asm aarch64 bugs (#305)

* Fix Asm aarch64 bug, RS2 occupies x18 register

* Fix Asm aarch64 bug, Version is u32, but read out of bounds

* Asm aarch64: x18 registers are not being pushed onto the stack

* Asm aarch64: modify the register call number for easy debugging

* Asm aarch64: reassign register

* Asm aarch64: Handling PREPCALL and POSTCALL

Author: joii2020

src/machine/asm/execute_aarch64.S

@@ -6,32 +6,32 @@
 
 #define MACHINE x0
 
-#define TEMP1 x8
-#define TEMP1w w8
-#define TEMP2 x9
-#define TEMP2w w9
-#define TEMP3 x10
-#define TEMP3w w10
-#define TEMP4 x11
-#define TEMP4w w11
-#define TEMP5 x12
-#define TEMP5w w12
-#define TRACE x13
-#define INST_PC x14
-#define INST_ARGS x15
+#define TEMP1 x9
+#define TEMP1w w9
+#define TEMP2 x10
+#define TEMP2w w10
+#define TEMP3 x11
+#define TEMP3w w11
+#define TEMP4 x12
+#define TEMP4w w12
+#define TEMP5 x13
+#define TEMP5w w13
+#define TRACE x19
+#define INST_PC x20
+#define INST_ARGS x21
 
-#define RD x16
-#define RS1 x17
-#define RS1w w17
-#define RS2 x18
-#define RS2w w18
-#define RS3 x19
-#define RS3w w19
-#define IMMEDIATE x20
-#define IMMEDIATEw w20
-#define FLAG x21
+#define RD x22
+#define RS1 x23
+#define RS1w w23
+#define RS2 x24
+#define RS2w w24
+#define RS3 x25
+#define RS3w w25
+#define IMMEDIATE x26
+#define IMMEDIATEw w26
+#define FLAG x27
 
-#define REGISTER_BASE x22
+#define REGISTER_BASE x28
 #define ZERO_VALUE xzr
 
 #ifdef __APPLE__
@@ -41,20 +41,14 @@
 #endif
 
 #define PREPCALL \
-  stp x0, x8, [sp, -96]! SEP \
-  stp x9, x10, [sp, 16] SEP \
-  stp x11, x12, [sp, 32] SEP \
-  stp x13, x14, [sp, 48] SEP \
-  stp x15, x16, [sp, 64] SEP \
-  stp x17, x18, [sp, 80]
+  stp x0, x9, [sp, -48]! SEP \
+  stp x10, x11, [sp, 16] SEP \
+  stp x12, x13, [sp, 32]
 
 #define POSTCALL \
-  ldp x17, x18, [sp, 80] SEP \
-  ldp x15, x16, [sp, 64] SEP \
-  ldp x13, x14, [sp, 48] SEP \
-  ldp x11, x12, [sp, 32] SEP \
-  ldp x9, x10, [sp, 16] SEP \
-  ldp x0, x8, [sp], 96
+  ldp x12, x13, [sp, 32] SEP \
+  ldp x10, x11, [sp, 16] SEP \
+  ldp x0, x9, [sp], 48
 
 #define REGISTER_ADDRESS(r) [REGISTER_BASE, r, lsl 3]
 #define ZERO_ADDRESS [REGISTER_BASE]
@@ -63,9 +57,9 @@
 #define PC_ADDRESS [MACHINE, CKB_VM_ASM_ASM_CORE_MACHINE_OFFSET_PC]
 #define VERSION_ADDRESS [MACHINE, CKB_VM_ASM_ASM_CORE_MACHINE_OFFSET_VERSION]
 
-#define LOAD_VERSION(r) \
+#define LOAD_VERSION(r, rw) \
   add r, MACHINE, CKB_VM_ASM_ASM_CORE_MACHINE_OFFSET_VERSION SEP \
-  ldr r, [r]
+  ldr rw, [r]
 
 #define WRITE_RD(v) \
   str v, REGISTER_ADDRESS(RD) SEP \
@@ -90,9 +84,9 @@
   asr TEMP1, TEMP1, 24 SEP \
   ubfx FLAG, TEMP1, 0, 8 SEP \
   asr TEMP1, TEMP1, 8 SEP \
-  ldr x9, [INST_PC] SEP \
+  ldr TEMP2, [INST_PC] SEP \
   add INST_PC, INST_PC, 8 SEP \
-  br x9
+  br TEMP2
 
 #define DECODE_R \
   ubfx RS1, TEMP1, 0, 8 SEP \
@@ -242,9 +236,12 @@ _ckb_vm_x64_execute:
 .globl ckb_vm_x64_execute
 ckb_vm_x64_execute:
 #endif
-  stp x19, x20, [sp, -48]!
+  stp x19, x20, [sp, -96]!
   stp x21, x22, [sp, 16]
-  stp x23, x30, [sp, 32]
+  stp x23, x24, [sp, 32]
+  stp x25, x26, [sp, 48]
+  stp x27, x28, [sp, 64]
+  stp x29, x30, [sp, 80]
   add REGISTER_BASE, MACHINE, CKB_VM_ASM_ASM_CORE_MACHINE_OFFSET_REGISTERS
 
 .CKB_VM_ASM_LABEL_OP_CUSTOM_TRACE_END:
@@ -494,8 +491,8 @@ ckb_vm_x64_execute:
   str RS1, PC_ADDRESS
   b .prepare_trace
 .CKB_VM_ASM_LABEL_OP_JALR:
-  LOAD_VERSION(TEMP5)
-  cmp TEMP5, 1
+  LOAD_VERSION(TEMP5, TEMP5w)
+  cmp TEMP5w, 1
   bge .CKB_VM_ASM_LABEL_OP_JALR_VERSION1
   b .CKB_VM_ASM_LABEL_OP_JALR_VERSION0
 .CKB_VM_ASM_LABEL_OP_JALR_VERSION0:
@@ -517,8 +514,8 @@ ckb_vm_x64_execute:
   str TEMP2, PC_ADDRESS
   b .prepare_trace
 .CKB_VM_ASM_LABEL_OP_LB:
-  LOAD_VERSION(TEMP5)
-  cmp TEMP5, 1
+  LOAD_VERSION(TEMP5, TEMP5w)
+  cmp TEMP5w, 1
   bge .CKB_VM_ASM_LABEL_OP_LB_VERSION1
   b .CKB_VM_ASM_LABEL_OP_LB_VERSION0
 .CKB_VM_ASM_LABEL_OP_LB_VERSION0:
@@ -538,8 +535,8 @@ ckb_vm_x64_execute:
   WRITE_RD(RS1)
   NEXT_INST
 .CKB_VM_ASM_LABEL_OP_LBU:
-  LOAD_VERSION(TEMP5)
-  cmp TEMP5, 1
+  LOAD_VERSION(TEMP5, TEMP5w)
+  cmp TEMP5w, 1
   bge .CKB_VM_ASM_LABEL_OP_LBU_VERSION1
   b .CKB_VM_ASM_LABEL_OP_LBU_VERSION0
 .CKB_VM_ASM_LABEL_OP_LBU_VERSION0:
@@ -559,8 +556,8 @@ ckb_vm_x64_execute:
   WRITE_RD(RS1)
   NEXT_INST
 .CKB_VM_ASM_LABEL_OP_LD:
-  LOAD_VERSION(TEMP5)
-  cmp TEMP5, 1
+  LOAD_VERSION(TEMP5, TEMP5w)
+  cmp TEMP5w, 1
   bge .CKB_VM_ASM_LABEL_OP_LD_VERSION1
   b .CKB_VM_ASM_LABEL_OP_LD_VERSION0
 .CKB_VM_ASM_LABEL_OP_LD_VERSION0:
@@ -580,8 +577,8 @@ ckb_vm_x64_execute:
   WRITE_RD(RS1)
   NEXT_INST
 .CKB_VM_ASM_LABEL_OP_LH:
-  LOAD_VERSION(TEMP5)
-  cmp TEMP5, 1
+  LOAD_VERSION(TEMP5, TEMP5w)
+  cmp TEMP5w, 1
   bge .CKB_VM_ASM_LABEL_OP_LH_VERSION1
   b .CKB_VM_ASM_LABEL_OP_LH_VERSION0
 .CKB_VM_ASM_LABEL_OP_LH_VERSION0:
@@ -601,8 +598,8 @@ ckb_vm_x64_execute:
   WRITE_RD(RS1)
   NEXT_INST
 .CKB_VM_ASM_LABEL_OP_LHU:
-  LOAD_VERSION(TEMP5)
-  cmp TEMP5, 1
+  LOAD_VERSION(TEMP5, TEMP5w)
+  cmp TEMP5w, 1
   bge .CKB_VM_ASM_LABEL_OP_LHU_VERSION1
   b .CKB_VM_ASM_LABEL_OP_LHU_VERSION0
 .CKB_VM_ASM_LABEL_OP_LHU_VERSION0:
@@ -632,8 +629,8 @@ ckb_vm_x64_execute:
   WRITE_RD(IMMEDIATE)
   NEXT_INST
 .CKB_VM_ASM_LABEL_OP_LW:
-  LOAD_VERSION(TEMP5)
-  cmp TEMP5, 1
+  LOAD_VERSION(TEMP5, TEMP5w)
+  cmp TEMP5w, 1
   bge .CKB_VM_ASM_LABEL_OP_LW_VERSION1
   b .CKB_VM_ASM_LABEL_OP_LW_VERSION0
 .CKB_VM_ASM_LABEL_OP_LW_VERSION0:
@@ -653,8 +650,8 @@ ckb_vm_x64_execute:
   WRITE_RD(RS1)
   NEXT_INST
 .CKB_VM_ASM_LABEL_OP_LWU:
-  LOAD_VERSION(TEMP5)
-  cmp TEMP5, 1
+  LOAD_VERSION(TEMP5, TEMP5w)
+  cmp TEMP5w, 1
   bge .CKB_VM_ASM_LABEL_OP_LWU_VERSION1
   b .CKB_VM_ASM_LABEL_OP_LWU_VERSION0
 .CKB_VM_ASM_LABEL_OP_LWU_VERSION0:
@@ -1612,7 +1609,10 @@ ckb_vm_x64_execute:
   mov x0, CKB_VM_ASM_RET_SLOWPATH
   b .exit
 .exit:
-  ldp x23, x30, [sp, 32]
+  ldp x29, x30, [sp, 80]
+  ldp x27, x28, [sp, 64]
+  ldp x25, x26, [sp, 48]
+  ldp x23, x24, [sp, 32]
   ldp x21, x22, [sp, 16]
-  ldp x19, x20, [sp], 48
+  ldp x19, x20, [sp], 96
   ret