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H. Peter Anvin
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x86: move the bytecode defintion into a separate file in x86/
At least three files (asm/assemble.c, disasm/disasm.c, and x86/insns.pl) depend on the bytecode defintions. It makes a lot more sense for them to live in an explicit documentation file in the x86/ directory. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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‎asm/assemble.c

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/*
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* assemble.c code generation for the Netwide Assembler
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*
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* Bytecode specification
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* ----------------------
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*
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*
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* Codes Mnemonic Explanation
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*
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* \0 terminates the code. (Unless it's a literal of course.)
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* \1..\4 that many literal bytes follow in the code stream
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* \5 add 4 to the primary operand number (b, low octdigit)
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* \6 add 4 to the secondary operand number (a, middle octdigit)
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* \7 add 4 to both the primary and the secondary operand number
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* \10..\13 a literal byte follows in the code stream, to be added
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* to the register value of operand 0..3
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* \14..\17 the position of index register operand in MIB (BND insns)
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* \20..\23 ib a byte immediate operand, from operand 0..3
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* \24..\27 ib,u a zero-extended byte immediate operand, from operand 0..3
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* \30..\33 iw a word immediate operand, from operand 0..3
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* \34..\37 iwd select between \3[0-3] and \4[0-3] depending on 16/32 bit
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* assembly mode or the operand-size override on the operand
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* \40..\43 id a long immediate operand, from operand 0..3
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* \44..\47 iwdq select between \3[0-3], \4[0-3] and \5[4-7]
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* depending on the address size of the instruction.
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* \50..\53 rel8 a byte relative operand, from operand 0..3
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* \54..\57 iq a qword immediate operand, from operand 0..3
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* \60..\63 rel16 a word relative operand, from operand 0..3
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* \64..\67 rel select between \6[0-3] and \7[0-3] depending on 16/32 bit
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* assembly mode or the operand-size override on the operand
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* \70..\73 rel32 a long relative operand, from operand 0..3
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* \74..\77 seg a word constant, from the _segment_ part of operand 0..3
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* \1ab /r a ModRM, calculated on EA in operand a, with the reg
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* field the register value of operand b.
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* \171\mab /mrb (e.g /3r0) a ModRM, with the reg field taken from operand a, and the m
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* and b fields set to the specified values.
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* \172\ab /is4 the register number from operand a in bits 7..4, with
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* the 4-bit immediate from operand b in bits 3..0.
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* \173\xab the register number from operand a in bits 7..4, with
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* the value b in bits 3..0.
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* \174..\177 the register number from operand 0..3 in bits 7..4, and
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* an arbitrary value in bits 3..0 (assembled as zero.)
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* \2ab /b a ModRM, calculated on EA in operand a, with the reg
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* field equal to digit b.
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* \240..\243 this instruction uses EVEX rather than REX or VEX/XOP, with the
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* V field taken from operand 0..3.
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* \250 this instruction uses EVEX rather than REX or VEX/XOP, with the
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* V field set to 1111b.
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*
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* EVEX prefixes are followed by the sequence:
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* \cm\wlp\tup where cm is:
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* cc 00m mmm
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* c = 2 for EVEX and mmmm is the M field (EVEX.P0[3:0])
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* and wlp is:
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* 00 wwl lpp
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* [l0] ll = 0 (.128, .lz)
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* [l1] ll = 1 (.256)
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* [l2] ll = 2 (.512)
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* [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
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*
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* [w0] ww = 0 for W = 0
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* [w1] ww = 1 for W = 1
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* [wig] ww = 2 for W don't care (always assembled as 0)
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* [ww] ww = 3 for W used as REX.W
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*
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* [p0] pp = 0 for no prefix
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* [60] pp = 1 for legacy prefix 60
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* [f3] pp = 2
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* [f2] pp = 3
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*
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* tup is tuple type for Disp8*N from %tuple_codes in insns.pl
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* (compressed displacement encoding)
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*
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* \254..\257 id,s a signed 32-bit operand to be extended to 64 bits.
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* \260..\263 this instruction uses VEX/XOP rather than REX, with the
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* V field taken from operand 0..3.
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* \270 this instruction uses VEX/XOP rather than REX, with the
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* V field set to 1111b.
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* VEX/XOP prefixes are followed by the sequence:
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* \tmm\wlp where mm is the M field; and wlp is:
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* 00 wwl lpp
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* [l0] ll = 0 for L = 0 (.128, .lz)
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* [l1] ll = 1 for L = 1 (.256)
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* [lig] ll = 2 for L don't care (always assembled as 0)
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*
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* [w0] ww = 0 for W = 0
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* [w1 ] ww = 1 for W = 1
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* [wig] ww = 2 for W don't care (always assembled as 0)
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* [ww] ww = 3 for W used as REX.W
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*
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* t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
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*
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* \271 hlexr instruction takes XRELEASE (F3) with or without lock
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* \272 hlenl instruction takes XACQUIRE/XRELEASE with or without lock
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* \273 hle instruction takes XACQUIRE/XRELEASE with lock only
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* \274..\277 ib,s a byte immediate operand, from operand 0..3, sign-extended
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* to the operand size (if o16/o32/o64 present) or the bit size
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* \310 a16 indicates fixed 16-bit address size, i.e. optional 0x67.
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* \311 a32 indicates fixed 32-bit address size, i.e. optional 0x67.
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* \312 adf (disassembler only) invalid with non-default address size.
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* \313 a64 indicates fixed 64-bit address size, 0x67 invalid.
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* \314 norexb (disassembler only) invalid with REX.B
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* \315 norexx (disassembler only) invalid with REX.X
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* \316 norexr (disassembler only) invalid with REX.R
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* \317 norexw (disassembler only) invalid with REX.W
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* \320 o16 indicates fixed 16-bit operand size, i.e. optional 0x66.
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* \321 o32 indicates fixed 32-bit operand size, i.e. optional 0x66.
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* \322 odf indicates that this instruction is only valid when the
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* operand size is the default (instruction to disassembler,
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* generates no code in the assembler)
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* \323 o64nw indicates fixed 64-bit operand size, REX on extensions only.
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* \324 o64 indicates 64-bit operand size requiring REX prefix.
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* \325 nohi instruction which always uses spl/bpl/sil/dil
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* \326 nof3 instruction not valid with 0xF3 REP prefix. Hint for
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disassembler only; for SSE instructions.
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* \331 norep instruction not valid with REP prefix. Hint for
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* disassembler only; for SSE instructions.
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* \332 f2i REP prefix (0xF2 byte) used as opcode extension.
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* \333 f3i REP prefix (0xF3 byte) used as opcode extension.
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* \334 rex.l LOCK prefix used as REX.R (used in non-64-bit mode)
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* \335 repe disassemble a rep (0xF3 byte) prefix as repe not rep.
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* \336 mustrep force a REP(E) prefix (0xF3) even if not specified.
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* \337 mustrepne force a REPNE prefix (0xF2) even if not specified.
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* \336-\337 are still listed as prefixes in the disassembler.
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* \340 resb reserve <operand 0> bytes of uninitialized storage.
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* Operand 0 had better be a segmentless constant.
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* \341 wait this instruction needs a WAIT "prefix"
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* \360 np no SSE prefix (== \364\331)
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* \361 66 SSE prefix (== \366\331)
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* \364 !osp operand-size prefix (0x66) not permitted
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* \365 !asp address-size prefix (0x67) not permitted
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* \366 operand-size prefix (0x66) used as opcode extension
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* \367 address-size prefix (0x67) used as opcode extension
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* \370,\371 jcc8 match only if operand 0 meets byte jump criteria.
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* jmp8 370 is used for Jcc, 371 is used for JMP.
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* \373 jlen assemble 0x03 if bits==16, 0x05 if bits==32;
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* used for conditional jump over longer jump
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* \374 vsibx|vm32x|vm64x this instruction takes an XMM VSIB memory EA
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* \375 vsiby|vm32y|vm64y this instruction takes an YMM VSIB memory EA
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* \376 vsibz|vm32z|vm64z this instruction takes an ZMM VSIB memory EA
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*/
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#include "compiler.h"

‎disasm/disasm.c

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/*
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* disasm.c where all the _work_ gets done in the Netwide Disassembler
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*
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* See x86/bytecode.txt for the definition of the instruction encoding
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* byte codes.
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*/
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#include "compiler.h"

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