change diff_rlgr1/3 to match rlgr1/3 on ending bits

jsorg71 · jsorg71 · commit 2d24fce3f8b5 · 2017-03-28T00:27:27.000-07:00
diff --git a/src/rfxencode_diff_rlgr1.c b/src/rfxencode_diff_rlgr1.c
@@ -240,6 +240,7 @@ rfx_encode_diff_rlgr1(sint16 *coef, uint8 *cdata, int cdata_size)
     if (bit_count > 0)
     {
         bits <<= 8 - bit_count;
+        bits |= ((1 << (8 - bit_count)) - 1) & *cdata;
         *cdata = bits;
         cdata++;
         bit_count = 0;
diff --git a/src/rfxencode_diff_rlgr3.c b/src/rfxencode_diff_rlgr3.c
@@ -277,6 +277,7 @@ rfx_encode_diff_rlgr3(sint16 *coef, uint8 *cdata, int cdata_size)
     if (bit_count > 0)
     {
         bits <<= 8 - bit_count;
+        bits |= ((1 << (8 - bit_count)) - 1) & *cdata;
         *cdata = bits;
         cdata++;
         bit_count = 0;

Original file line number	Diff line number	Diff line change
`@@ -240,6 +240,7 @@ rfx_encode_diff_rlgr1(sint16 coef, uint8 cdata, int cdata_size)`
`240`	`240`	`if (bit_count > 0)`
`241`	`241`	`{`
`242`	`242`	`bits <<= 8 - bit_count;`
	`243`	`+ bits \|= ((1 << (8 - bit_count)) - 1) & *cdata;`
`243`	`244`	`*cdata = bits;`
`244`	`245`	`cdata++;`
`245`	`246`	`bit_count = 0;`
Original file line number	Diff line number	Diff line change
`@@ -277,6 +277,7 @@ rfx_encode_diff_rlgr3(sint16 coef, uint8 cdata, int cdata_size)`
`277`	`277`	`if (bit_count > 0)`
`278`	`278`	`{`
`279`	`279`	`bits <<= 8 - bit_count;`
	`280`	`+ bits \|= ((1 << (8 - bit_count)) - 1) & *cdata;`
`280`	`281`	`*cdata = bits;`
`281`	`282`	`cdata++;`
`282`	`283`	`bit_count = 0;`