Add SystemVerilog function/task_declaration to context

MinhTran0911 · lewis6991 · commit ebd9a5a7b1c6 · 2025-02-17T12:41:04.000Z
diff --git a/queries/verilog/context.scm b/queries/verilog/context.scm
@@ -2,3 +2,5 @@
 (conditional_statement) @context
 (loop_generate_construct) @context
 (hierarchical_instance) @context
+(function_declaration) @context
+(task_declaration) @context
