@@ -1495,6 +1495,25 @@ OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) {
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}
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}
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+ copy_lrg = _lrg_map.find (lrg._copy_bias2 );
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+ if (copy_lrg != 0 ) {
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+ // If he has a color,
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+ if (!_ifg->_yanked ->test (copy_lrg)) {
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+ OptoReg::Name reg = lrgs (copy_lrg).reg ();
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+ // And it is legal for you,
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+ if (is_legal_reg (lrg, reg, chunk))
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+ return reg;
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+ } else if ( chunk == 0 ) {
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+ // Choose a color which is legal for him
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+ RegMask tempmask = lrg.mask ();
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+ tempmask.AND (lrgs (copy_lrg).mask ());
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+ tempmask.clear_to_sets (lrg.num_regs ());
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+ OptoReg::Name reg = find_first_set (lrg, tempmask, chunk);
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+ if (OptoReg::is_valid (reg))
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+ return reg;
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+ }
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+ }
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+
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// If no bias info exists, just go with the register selection ordering
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if (lrg._is_vector || lrg.num_regs () == 2 || lrg.is_scalable ()) {
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// Find an aligned set
@@ -1617,6 +1636,39 @@ uint PhaseChaitin::Select( ) {
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}
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}
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}
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+
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+ auto is_commutative_oper = [](MachNode* def) {
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+ switch (def->ideal_Opcode ()) {
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+ case Op_AddI: case Op_AddL:
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+ case Op_MulI: case Op_MulL:
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+ case Op_XorI: case Op_XorL:
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+ case Op_OrI: case Op_OrL:
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+ case Op_AndI: case Op_AndL:
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+ return true ;
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+ default :
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+ return false ;
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+ }
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+ };
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+
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+ if (UseAPX) {
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+ Node* def = lrg->_def ;
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+ if (def->is_Mach ()) {
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+ MachNode* mdef = def->as_Mach ();
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+ for (uint i = mdef->oper_input_base (); i < def->req (); i++) {
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+ uint lruseidx = _lrg_map.find (def->in (i));
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+ // If a def does not interfere with any of its use's def
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+ // then bias def color towards its it.
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+ if (lruseidx != 0 && _ifg->test_edge_sq (lidx, lruseidx) == 0 ) {
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+ if (lrg->_copy_bias == 0 ) {
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+ lrg->_copy_bias = lruseidx;
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+ } else if (lrg->_copy_bias2 == 0 && is_commutative_oper (mdef)) {
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+ lrg->_copy_bias2 = lruseidx;
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+ }
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+ }
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+ }
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+ }
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+ }
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+
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// assert(is_allstack == lrg->mask().is_AllStack(), "nbrs must not change AllStackedness");
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// Aligned pairs need aligned masks
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assert (!lrg->_is_vector || !lrg->_fat_proj , " sanity" );
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