As in spec, EEAR register should save the instruction fetch VA when illegal instruction exception. We should change code in mor1kx_ctrl_cappuccino.v as follow. ```verilog always @(posedge clk `OR_ASYNC_RST) if (rst) spr_eear <= {OPTION_OPERAND_WIDTH{1'b0}}; else if (/*padv_ctrl & exception*/ exception_re) begin if (except_ibus_err_i | except_itlb_miss_i | except_ipagefault_i | except_illegal_i) spr_eear <= pc_ctrl_i; else if (except_dbus_i | except_dtlb_miss_i | except_dpagefault_i | except_align_i) spr_eear <= ctrl_lsu_adr_i; end ```