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FaragElsayed2FaragElsayed2
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Merge pull request google#55 from mabrains/mos_iv_regression
Mos iv regression
2 parents d2a2060 + 8169911 commit 64e640d

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‎models/ngspice/testing/regression/mos_cv/device_netlists_Cgc/nmos_3p3_cv.spice‎ renamed to ‎models/ngspice/testing/regression/mos_cv/device_netlists_Cgc/nfet_03v3.spice‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ vbs S_tn 0 dc=0
3434
* pd = (int((nf+1)/2) * width/nf + 0.24)*2 = 200.48u
3535

3636
* circuit
37-
mn D_tn G_tn S_tn S_tn nfet_03v3 W = {{width}}u L = {{length}}u nf={{nf}} ad= 24u pd=200.48u as=24u ps=200.48u
37+
mn 0 G_tn 0 S_tn nfet_03v3 W = {{width}}u L = {{length}}u nf={{nf}} ad= 24u pd=200.48u as=24u ps=200.48u
3838

3939
.control
4040
set filetype=ascii
@@ -64,7 +64,7 @@ foreach t 25
6464

6565
print @mn[cgb]
6666

67-
wrdata nfet_03v3_cv/simulated_Cgc/{{i}}_simulated_W{{width}}_L{{length}}.csv {@mn[cgb]*1e15}
67+
wrdata mos_cv_regr/nfet_03v3/simulated_Cgc/simulated_W{{width}}_L{{length}}.csv {@mn[cgb]*1e15}
6868

6969
reset
7070
let vbs_counter = vbs_counter + 1

‎models/ngspice/testing/regression/mos_cv/device_netlists_Cgc/nfet_06v0.spice‎

Lines changed: 74 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,74 @@
1+
***************************
2+
** nfet_06v0
3+
***************************
4+
* Copyright 2022 Efabless Corporation
5+
*
6+
* Licensed under the Apache License, Version 2.0 (the "License");
7+
* you may not use this file except in compliance with the License.
8+
* You may obtain a copy of the License at
9+
*
10+
* http://www.apache.org/licenses/LICENSE-2.0
11+
*
12+
* Unless required by applicable law or agreed to in writing, software
13+
* distributed under the License is distributed on an "AS IS" BASIS,
14+
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15+
* See the License for the specific language governing permissions and
16+
* limitations under the License.
17+
** library calling
18+
19+
.include "../../../design.ngspice"
20+
.lib "../../../sm141064.ngspice" typical
21+
22+
23+
** Circuit Description **
24+
* power supply
25+
vds D_tn 0 dc=0
26+
vgs G_tn 0 dc=6
27+
vbs S_tn 0 dc=0
28+
29+
.temp 25
30+
.options tnom=25
31+
32+
*l_diff_min = 0.24
33+
* ad = int((nf+1)/2) * width/nf * 0.24 = 24u
34+
* pd = (int((nf+1)/2) * width/nf + 0.24)*2 = 200.48u
35+
36+
* circuit
37+
mn 0 G_tn 0 S_tn nfet_06v0 W = {{width}}u L = {{length}}u nf={{nf}} ad= 24u pd=200.48u as=24u ps=200.48u
38+
39+
.control
40+
set filetype=ascii
41+
42+
let vgs_min = -6
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let vgs_step = 0.1
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let vgs_max = 6
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compose vbs_vector start=0 stop=-3 step=-1
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set appendwrite
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foreach t 25
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let vbs_counter = 0
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while vbs_counter < length(vbs_vector)
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option TEMP=25
55+
alter vbs = vbs_vector[vbs_counter]
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57+
save @mn[vs] @mn[vgs] @mn[id] @mn[cgb]
58+
*******************
59+
** simulation part
60+
*******************
61+
DC vgs $&vgs_min $&vgs_max $&vgs_step
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63+
* ** parameters calculation
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print @mn[cgb]
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67+
wrdata mos_cv_regr/nfet_06v0/simulated_Cgc/simulated_W{{width}}_L{{length}}.csv {@mn[cgb]*1e15}
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69+
reset
70+
let vbs_counter = vbs_counter + 1
71+
end
72+
end
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.endc
74+
.end

‎models/ngspice/testing/regression/mos_cv/device_netlists_Cgc/nfet_06v0_nvt.spice‎

Lines changed: 74 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,74 @@
1+
***************************
2+
** nfet_06v0
3+
***************************
4+
* Copyright 2022 Efabless Corporation
5+
*
6+
* Licensed under the Apache License, Version 2.0 (the "License");
7+
* you may not use this file except in compliance with the License.
8+
* You may obtain a copy of the License at
9+
*
10+
* http://www.apache.org/licenses/LICENSE-2.0
11+
*
12+
* Unless required by applicable law or agreed to in writing, software
13+
* distributed under the License is distributed on an "AS IS" BASIS,
14+
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15+
* See the License for the specific language governing permissions and
16+
* limitations under the License.
17+
** library calling
18+
19+
.include "../../../design.ngspice"
20+
.lib "../../../sm141064.ngspice" typical
21+
22+
23+
** Circuit Description **
24+
* power supply
25+
vds D_tn 0 dc=0
26+
vgs G_tn 0 dc=6
27+
vbs S_tn 0 dc=0
28+
29+
.temp 25
30+
.options tnom=25
31+
32+
*l_diff_min = 0.24
33+
* ad = int((nf+1)/2) * width/nf * 0.24 = 24u
34+
* pd = (int((nf+1)/2) * width/nf + 0.24)*2 = 200.48u
35+
36+
* circuit
37+
mn 0 G_tn 0 S_tn nfet_06v0_nvt W = {{width}}u L = {{length}}u nf={{nf}} ad= 24u pd=200.48u as=24u ps=200.48u
38+
39+
.control
40+
set filetype=ascii
41+
42+
let vgs_min = -6
43+
let vgs_step = 0.1
44+
let vgs_max = 6
45+
46+
compose vbs_vector start=0 stop=-3 step=-1
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48+
set appendwrite
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50+
foreach t 25
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52+
let vbs_counter = 0
53+
while vbs_counter < length(vbs_vector)
54+
option TEMP=25
55+
alter vbs = vbs_vector[vbs_counter]
56+
57+
save @mn[vs] @mn[vgs] @mn[id] @mn[cgb]
58+
*******************
59+
** simulation part
60+
*******************
61+
DC vgs $&vgs_min $&vgs_max $&vgs_step
62+
63+
* ** parameters calculation
64+
65+
print @mn[cgb]
66+
67+
wrdata mos_cv_regr/nfet_06v0_nvt/simulated_Cgc/simulated_W{{width}}_L{{length}}.csv {@mn[cgb]*1e15}
68+
69+
reset
70+
let vbs_counter = vbs_counter + 1
71+
end
72+
end
73+
.endc
74+
.end

‎models/ngspice/testing/regression/mos_cv/device_netlists_Cgc/pmos_3p3_cv.spice‎ renamed to ‎models/ngspice/testing/regression/mos_cv/device_netlists_Cgc/pfet_03v3.spice‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ vbs S_tn 0 dc=0
3434
* pd = (int((nf+1)/2) * width/nf + 0.24)*2 = 200.48u
3535

3636
* circuit
37-
mn D_tn G_tn S_tn S_tn pfet_03v3 W = {{width}}u L = {{length}}u nf={{nf}} ad= 24u pd=200.48u as=24u ps=200.48u
37+
mn 0 G_tn 0 S_tn pfet_03v3 W = {{width}}u L = {{length}}u nf={{nf}} ad= 24u pd=200.48u as=24u ps=200.48u
3838

3939
.control
4040
set filetype=ascii
@@ -64,7 +64,7 @@ foreach t 25
6464

6565
print @mn[cgb]
6666

67-
wrdata pfet_03v3_cv/simulated_Cgc/{{i}}_simulated_W{{width}}_L{{length}}.csv {@mn[cgb]*1e15}
67+
wrdata mos_cv_regr/pfet_03v3/simulated_Cgc/simulated_W{{width}}_L{{length}}.csv {@mn[cgb]*1e15}
6868

6969
reset
7070
let vbs_counter = vbs_counter + 1

‎models/ngspice/testing/regression/mos_cv/device_netlists_Cgc/pfet_06v0.spice‎

Lines changed: 74 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,74 @@
1+
***************************
2+
** pfet_03v3_cv
3+
***************************
4+
* Copyright 2022 Efabless Corporation
5+
*
6+
* Licensed under the Apache License, Version 2.0 (the "License");
7+
* you may not use this file except in compliance with the License.
8+
* You may obtain a copy of the License at
9+
*
10+
* http://www.apache.org/licenses/LICENSE-2.0
11+
*
12+
* Unless required by applicable law or agreed to in writing, software
13+
* distributed under the License is distributed on an "AS IS" BASIS,
14+
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15+
* See the License for the specific language governing permissions and
16+
* limitations under the License.
17+
** library calling
18+
19+
.include "../../../design.ngspice"
20+
.lib "../../../sm141064.ngspice" typical
21+
22+
23+
** Circuit Description **
24+
* power supply
25+
vds D_tn 0 dc=0
26+
vgs G_tn 0 dc=6
27+
vbs S_tn 0 dc=0
28+
29+
.temp 25
30+
.options tnom=25
31+
32+
*l_diff_min = 0.24
33+
* ad = int((nf+1)/2) * width/nf * 0.24 = 24u
34+
* pd = (int((nf+1)/2) * width/nf + 0.24)*2 = 200.48u
35+
36+
* circuit
37+
mn 0 G_tn 0 S_tn pfet_06v0 W = {{width}}u L = {{length}}u nf={{nf}} ad= 24u pd=200.48u as=24u ps=200.48u
38+
39+
.control
40+
set filetype=ascii
41+
42+
let vgs_min = -6
43+
let vgs_step = 0.1
44+
let vgs_max = 6
45+
46+
compose vbs_vector start=0 stop=3. step=1
47+
48+
set appendwrite
49+
50+
foreach t 25
51+
52+
let vbs_counter = 0
53+
while vbs_counter < length(vbs_vector)
54+
option TEMP=25
55+
alter vbs = vbs_vector[vbs_counter]
56+
57+
save @mn[vs] @mn[vgs] @mn[id] @mn[cgb]
58+
*******************
59+
** simulation part
60+
*******************
61+
DC vgs $&vgs_min $&vgs_max $&vgs_step
62+
63+
* ** parameters calculation
64+
65+
print @mn[cgb]
66+
67+
wrdata mos_cv_regr/pfet_06v0/simulated_Cgc/simulated_W{{width}}_L{{length}}.csv {@mn[cgb]*1e15}
68+
69+
reset
70+
let vbs_counter = vbs_counter + 1
71+
end
72+
end
73+
.endc
74+
.end

‎models/ngspice/testing/regression/mos_cv/device_netlists_Cgd/nmos_3p3_cv.spice‎ renamed to ‎models/ngspice/testing/regression/mos_cv/device_netlists_Cgd/nfet_03v3.spice‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@
2424
* power supply
2525
vds D_tn 0 dc=3.3
2626
vgs G_tn 0 dc=3.3
27-
vs S_tn 0 dc=0.2
27+
vs S_tn 0 dc=0
2828

2929
.temp 25
3030
.options tnom=25
@@ -34,7 +34,7 @@ vs S_tn 0 dc=0.2
3434
* pd = (int((nf+1)/2) * width/nf + 0.24)*2 = 200.48u
3535

3636
* circuit
37-
mn D_tn G_tn S_tn S_tn nfet_03v3 W = 200u L = 0.28u nf=20 ad= 24u pd=200.48u as=24u ps=200.48u
37+
mn D_tn G_tn S_tn S_tn nfet_03v3 W = {{width}}u L = {{length}}u nf={{nf}} ad= 24u pd=200.48u as=24u ps=200.48u
3838

3939
.control
4040
set filetype=ascii
@@ -64,7 +64,7 @@ foreach t 25
6464

6565
print @mn[cgd]
6666

67-
wrdata nfet_03v3_cv/simulated_Cgd/{{i}}_simulated_W{{width}}_L{{length}}.csv {@mn[cgd]*1e15}
67+
wrdata mos_cv_regr/nfet_03v3/simulated_Cgd/simulated_W{{width}}_L{{length}}.csv {@mn[cgd]*1e15}
6868

6969
reset
7070
let vgs_counter = vgs_counter + 1

‎models/ngspice/testing/regression/mos_cv/device_netlists_Cgd/nfet_06v0.spice‎

Lines changed: 74 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,74 @@
1+
***************************
2+
** nfet_03v3_cv
3+
***************************
4+
* Copyright 2022 Efabless Corporation
5+
*
6+
* Licensed under the Apache License, Version 2.0 (the "License");
7+
* you may not use this file except in compliance with the License.
8+
* You may obtain a copy of the License at
9+
*
10+
* http://www.apache.org/licenses/LICENSE-2.0
11+
*
12+
* Unless required by applicable law or agreed to in writing, software
13+
* distributed under the License is distributed on an "AS IS" BASIS,
14+
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15+
* See the License for the specific language governing permissions and
16+
* limitations under the License.
17+
** library calling
18+
19+
.include "../../../design.ngspice"
20+
.lib "../../../sm141064.ngspice" typical
21+
22+
23+
** Circuit Description **
24+
* power supply
25+
vds D_tn 0 dc=6
26+
vgs G_tn 0 dc=6
27+
vs S_tn 0 dc=0
28+
29+
.temp 25
30+
.options tnom=25
31+
32+
*l_diff_min = 0.24
33+
* ad = int((nf+1)/2) * width/nf * 0.24 = 24u
34+
* pd = (int((nf+1)/2) * width/nf + 0.24)*2 = 200.48u
35+
36+
* circuit
37+
mn D_tn G_tn S_tn S_tn nfet_06v0 W = {{width}}u L = {{length}}u nf={{nf}} ad= 24u pd=200.48u as=24u ps=200.48u
38+
39+
.control
40+
set filetype=ascii
41+
42+
let vds_min = 0
43+
let vds_step = 0.1
44+
let vds_max = 6
45+
46+
compose vgs_vector start=0 stop=6 step=2
47+
48+
set appendwrite
49+
50+
foreach t 25
51+
52+
let vgs_counter = 0
53+
while vgs_counter < length(vgs_vector)
54+
option TEMP=25
55+
alter vgs = vgs_vector[vgs_counter]
56+
57+
save @mn[vds] @mn[vgs] @mn[id] @mn[cgd]
58+
*******************
59+
** simulation part
60+
*******************
61+
DC vds $&vds_min $&vds_max $&vds_step
62+
63+
* ** parameters calculation
64+
65+
print @mn[cgd]
66+
67+
wrdata mos_cv_regr/nfet_06v0/simulated_Cgd/simulated_W{{width}}_L{{length}}.csv {@mn[cgd]*1e15}
68+
69+
reset
70+
let vgs_counter = vgs_counter + 1
71+
end
72+
end
73+
.endc
74+
.end

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