From a71b7b5341fcd089cc5af3dd7c3037b60989a493 Mon Sep 17 00:00:00 2001 From: Kimish Patel Date: Thu, 1 May 2025 15:25:20 -0700 Subject: [PATCH 1/5] [WIP] update apple soc info Summary: Test Plan: Reviewers: Subscribers: Tasks: Tags: [ghstack-poisoned] --- src/arm/mach/init.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/src/arm/mach/init.c b/src/arm/mach/init.c index c4e6521b..cbaf94f2 100644 --- a/src/arm/mach/init.c +++ b/src/arm/mach/init.c @@ -27,6 +27,48 @@ #ifndef CPUFAMILY_ARM_AVALANCHE_BLIZZARD #define CPUFAMILY_ARM_AVALANCHE_BLIZZARD 0xDA33D83D #endif +// Following are copied over from ncnn/src/cpu.cpp +// A15 / M2 +#ifndef CPUFAMILY_ARM_AVALANCHE_BLIZZARD +#define CPUFAMILY_ARM_AVALANCHE_BLIZZARD 0xda33d83d +#endif +// A16 +#ifndef CPUFAMILY_ARM_EVEREST_SAWTOOTH +#define CPUFAMILY_ARM_EVEREST_SAWTOOTH 0x8765edea +#endif +// A17 +#ifndef CPUFAMILY_ARM_COLL +#define CPUFAMILY_ARM_COLL 0x2876f5b5 +#endif +// A18 +#ifndef CPUFAMILY_ARM_TUPAI +#define CPUFAMILY_ARM_TUPAI 0x204526d0 +#endif +// A18 Pro +#ifndef CPUFAMILY_ARM_TAHITI +#define CPUFAMILY_ARM_TAHITI 0x75d4acb9 +#endif +// M3 +#ifndef CPUFAMILY_ARM_IBIZA +#define CPUFAMILY_ARM_IBIZA 0xfa33415e +#endif +// M3 Pro +#ifndef CPUFAMILY_ARM_LOBOS +#define CPUFAMILY_ARM_LOBOS 0x5f4dea93 +#endif +// M3 Max +#ifndef CPUFAMILY_ARM_PALMA +#define CPUFAMILY_ARM_PALMA 0x72015832 +#endif +// M4 +#ifndef CPUFAMILY_ARM_DONAN +#define CPUFAMILY_ARM_DONAN 0x6f5129ac +#endif +// M4 Pro / M4 Max +#ifndef CPUFAMILY_ARM_BRAVA +#define CPUFAMILY_ARM_BRAVA 0x17d5b93a +#endif +#endif // __APPLE__ struct cpuinfo_arm_isa cpuinfo_isa = { .aes = true, From bb44bb9a1eb130fe6df3901c879029918b99c0cb Mon Sep 17 00:00:00 2001 From: Kimish Patel Date: Tue, 27 May 2025 18:01:09 -0700 Subject: [PATCH 2/5] Update on "[WIP] update apple soc info" Summary: Test Plan: Reviewers: Subscribers: Tasks: Tags: [ghstack-poisoned] --- include/cpuinfo.h | 16 ++++++++++++++++ src/arm/mach/init.c | 22 ++++++++++++++++++---- 2 files changed, 34 insertions(+), 4 deletions(-) diff --git a/include/cpuinfo.h b/include/cpuinfo.h index 5f93819e..bf546227 100644 --- a/include/cpuinfo.h +++ b/include/cpuinfo.h @@ -581,6 +581,22 @@ enum cpuinfo_uarch { cpuinfo_uarch_avalanche = 0x0070010D, /** Apple A15 / M2 processor (little cores). */ cpuinfo_uarch_blizzard = 0x0070010E, + /** Apple A16 processor (big cores). */ + cpuinfo_uarch_everest = 0x00700200, + /** Apple A16 processor (little cores). */ + cpuinfo_uarch_sawtooth = 0x00700201, + /** Apple A17 processor (big cores). */ + cpuinfo_uarch_coll_everest = 0x00700202, + /** Apple A17 processor (little cores). */ + cpuinfo_uarch_coll_sawtooth = 0x00700203, + /** Apple A18 processor (big cores). */ + cpuinfo_uarch_tupai_everest = 0x00700204, + /** Apple A18 processor (little cores). */ + cpuinfo_uarch_tupai_sawtooth = 0x00700205, + /** Apple A18 pro processor (big cores). */ + cpuinfo_uarch_tahiti_everest = 0x00700206, + /** Apple A18 pro processor (little cores). */ + cpuinfo_uarch_tahiti_sawtooth = 0x00700207, /** Cavium ThunderX. */ cpuinfo_uarch_thunderx = 0x00800100, diff --git a/src/arm/mach/init.c b/src/arm/mach/init.c index cbaf94f2..9fa560a9 100644 --- a/src/arm/mach/init.c +++ b/src/arm/mach/init.c @@ -28,10 +28,6 @@ #define CPUFAMILY_ARM_AVALANCHE_BLIZZARD 0xDA33D83D #endif // Following are copied over from ncnn/src/cpu.cpp -// A15 / M2 -#ifndef CPUFAMILY_ARM_AVALANCHE_BLIZZARD -#define CPUFAMILY_ARM_AVALANCHE_BLIZZARD 0xda33d83d -#endif // A16 #ifndef CPUFAMILY_ARM_EVEREST_SAWTOOTH #define CPUFAMILY_ARM_EVEREST_SAWTOOTH 0x8765edea @@ -48,6 +44,8 @@ #ifndef CPUFAMILY_ARM_TAHITI #define CPUFAMILY_ARM_TAHITI 0x75d4acb9 #endif +// For M3/M4 we need to populate more information about +// efficiency and perf cores. // M3 #ifndef CPUFAMILY_ARM_IBIZA #define CPUFAMILY_ARM_IBIZA 0xfa33415e @@ -135,6 +133,22 @@ static enum cpuinfo_uarch decode_uarch(uint32_t cpu_family, uint32_t core_index, case CPUFAMILY_ARM_AVALANCHE_BLIZZARD: /* Hexa-core: 2x Avalanche + 4x Blizzard */ return core_index + 4 < core_count ? cpuinfo_uarch_avalanche : cpuinfo_uarch_blizzard; + case CPUFAMILY_ARM_EVEREST_SAWTOOTH: + /* Hexa-core: 2x Avalanche + 4x Blizzard */ + return core_index + 4 < core_count ? cpuinfo_uarch_everest : cpuinfo_uarch_sawtooth; + return core_index + 4 < core_count ? cpuinfo_uarch_avalanche : cpuinfo_uarch_blizzard; + case CPUFAMILY_ARM_COLL: + /* Hexa-core: 2x Avalanche + 4x Blizzard */ + return core_index + 4 < core_count ? cpuinfo_uarch_coll_everest : cpuinfo_uarch_coll_sawtooth; + + case CPUFAMILY_ARM_TUPAI: + /* Hexa-core: 2x Avalanche + 4x Blizzard */ + return core_index + 4 < core_count ? cpuinfo_uarch_tupai_everest : cpuinfo_uarch_tupai_sawtooth; + + case CPUFAMILY_ARM_TAHITI: + /* Hexa-core: 2x Avalanche + 4x Blizzard */ + return core_index + 4 < core_count ? cpuinfo_uarch_tahiti_everest : cpuinfo_uarch_tahiti_sawtooth; + default: /* Use hw.cpusubtype for detection */ break; From 8a7ea9d60b7b90234aead0a22ecc92a3305c77db Mon Sep 17 00:00:00 2001 From: Kimish Patel Date: Tue, 27 May 2025 18:06:46 -0700 Subject: [PATCH 3/5] Update on "[WIP] update apple soc info" Summary: Test Plan: Reviewers: Subscribers: Tasks: Tags: [ghstack-poisoned] --- src/arm/mach/init.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/arm/mach/init.c b/src/arm/mach/init.c index 9fa560a9..55ac341c 100644 --- a/src/arm/mach/init.c +++ b/src/arm/mach/init.c @@ -66,7 +66,6 @@ #ifndef CPUFAMILY_ARM_BRAVA #define CPUFAMILY_ARM_BRAVA 0x17d5b93a #endif -#endif // __APPLE__ struct cpuinfo_arm_isa cpuinfo_isa = { .aes = true, From 8f9b523a0daf35925529a3513ab001ef531669c6 Mon Sep 17 00:00:00 2001 From: Kimish Patel Date: Wed, 28 May 2025 09:42:54 -0700 Subject: [PATCH 4/5] Update on "[WIP] update apple soc info" Summary: Test Plan: Reviewers: Subscribers: Tasks: Tags: [ghstack-poisoned] --- tools/cpu-info.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/tools/cpu-info.c b/tools/cpu-info.c index ca3ebfad..5f8a1158 100644 --- a/tools/cpu-info.c +++ b/tools/cpu-info.c @@ -270,6 +270,22 @@ static const char* uarch_to_string(enum cpuinfo_uarch uarch) { return "Avalanche"; case cpuinfo_uarch_blizzard: return "Blizzard"; + case cpuinfo_uarch_everest: + return "Everest"; + case cpuinfo_uarch_sawtooth: + return "Sawtooth"; + case cpuinfo_uarch_coll_everest: + return "Coll_Everest"; + case cpuinfo_uarch_coll_sawtooth: + return "Coll_Sawtooth"; + case cpuinfo_uarch_tupai_everest: + return "Tupai_Everest"; + case cpuinfo_uarch_tupai_sawtooth: + return "Tupai_Sawtooth"; + case cpuinfo_uarch_tahiti_everest: + return "Tahiti_Everest"; + case cpuinfo_uarch_tahiti_sawtooth: + return "Tahiti_Sawtooth"; case cpuinfo_uarch_thunderx: return "ThunderX"; case cpuinfo_uarch_thunderx2: From 23759e8706ccbded03c4fc92da468f64477c26d5 Mon Sep 17 00:00:00 2001 From: Kimish Patel Date: Wed, 28 May 2025 09:50:23 -0700 Subject: [PATCH 5/5] Update on "update apple soc info" Summary: Test Plan: Reviewers: Subscribers: Tasks: Tags: [ghstack-poisoned] --- src/arm/mach/init.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/arm/mach/init.c b/src/arm/mach/init.c index 55ac341c..2980f23a 100644 --- a/src/arm/mach/init.c +++ b/src/arm/mach/init.c @@ -146,7 +146,8 @@ static enum cpuinfo_uarch decode_uarch(uint32_t cpu_family, uint32_t core_index, case CPUFAMILY_ARM_TAHITI: /* Hexa-core: 2x Avalanche + 4x Blizzard */ - return core_index + 4 < core_count ? cpuinfo_uarch_tahiti_everest : cpuinfo_uarch_tahiti_sawtooth; + return core_index + 4 < core_count ? cpuinfo_uarch_tahiti_everest + : cpuinfo_uarch_tahiti_sawtooth; default: /* Use hw.cpusubtype for detection */