Implement `IgnoreExtraWires`

[mpharrigan]

Sometimes, you need to expose a consistent signature whether or not you're using all the registers that the interface demands. The AutoPartition bloq helps you take a register of a given dtype, split it up (partition it), optionally ignore some of the partitions, and then puts it back together. What if you don't need the partitioning part and just need the ignoring part? We could have a bookkeeping bloq that just indexes into an existing, shaped register.

[mpharrigan]

I whipped up the following as a working example of what I imagine

from typing import Dict

import attrs
from qualtran import Bloq, Signature, QDType, Register


@attrs.frozen
class IgnoreExtraWires(Bloq):
    subbloq: Bloq
    subregname: str
    subdtype: QDType
    M: int
    i: int

    @property
    def signature(self) -> 'Signature':
        return Signature([Register('reg', dtype=self.subdtype, shape=(self.M,))])

    def build_composite_bloq(self, bb: 'BloqBuilder', reg) -> Dict[str, 'SoquetT']:
        reg[self.i] = bb.add(self.subbloq, **{self.subregname: reg[self.i]})
        return {'reg': reg}

example

n = 5
m = 4
b = IgnoreExtraWires(subbloq=my_bloq(), subregname='component', subdtype=QInt(n), M=m, i=1)
show_bloq(b.decompose_bloq())