A synchronous FIFO refers to a FIFO design where data values are written sequentially into a memory array using a clock signal, and the data values are sequentially read out from the memory array using the same clock signal

BLOCK DIAGRAM

ARCHITECTURE DIAGAM

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DATA_W 128 // Data width

DEPTH 1024 // Depth of FIFO

UPP_TH 4 // Upper threshold to generate Almost-full

LOW_TH 2 // Lower threshold to generate Almost-empty

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Here is the EDA link and execute it in order to get better understanding