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Merge pull request #30 from rameloni/update-chisel-version
Bump chisel v6.4.3-tywaves (fork) and improve examples
2 parents 52b9eba + 5f16d0e commit e418da6

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‎Makefile

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3,14 +3,14 @@
33
TYWAVES_SURFER_NAME=surfer-tywaves-demo
44
TYWAVES_SURFER_REPO=https://gitlab.com/rameloni/${TYWAVES_SURFER_NAME}.git
55
TYWAVES_SURFER_VERSION=0.3.2
6-
TYWAVES_SURFER_TAG=v${TYWAVES_SURFER_VERSION}-tywaves-dev-SNAPSHOT
6+
TYWAVES_SURFER_TAG=v${TYWAVES_SURFER_VERSION}-tywaves-SNAPSHOT
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TYWAVES_SURFER_BIN=surfer-tywaves
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TYWAVES_SURFER_TARGET_NAME=${TYWAVES_SURFER_BIN}-${TYWAVES_SURFER_VERSION}
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TYWAVES_SURFER_INSTALL_PATH=$(HOME)/.cargo/bin/
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# Chisel information
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CHISEL_FORK_REPO=https://github.com/rameloni/chisel.git
13-
CHISEL_FORK_TAG=v6.4.2-tywaves-SNAPSHOT
13+
CHISEL_FORK_TAG=v6.4.3-tywaves-SNAPSHOT
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1515
# Circt (firtool) information
1616
CIRCT_FIRTOOL_ZIP_NAME=firtool-bin-linux-x64.tar.gz
@@ -48,7 +48,7 @@ install-chisel-fork: create-tmp
4848
@cd tmp/chisel && sbt "unipublish / publishLocal"
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5050
install-tywaves-chisel-api: install-chisel-fork
51-
@sbt publishLocal
51+
@sbt reload && sbt compile && sbt publishLocal
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clean-firtool-fork-bin:
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$(RM) tmp/$(CIRCT_FIRTOOL_ZIP_NAME)*

‎README.md

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,8 @@ The full project depends on the following tools. To install them, please check t
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- [Make](https://www.gnu.org/software/make/)
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- [Scala and sbt](https://docs.scala-lang.org/getting-started/sbt-track/getting-started-with-scala-and-sbt-on-the-command-line.html)
56-
and [scala-cli](https://scala-cli.virtuslab.org/install)
56+
and [scala-cli](https://scala-cli.virtuslab.org/install) (_Note: Java versions prior to Java 11, tywaves may not work
57+
correctly_)
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- [Rust](https://www.rust-lang.org/tools/install)
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- `openssl` for installing the waveform
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gui ([instructions](https://gitlab.com/rameloni/surfer-tywaves-demo#compiling-from-source))
@@ -234,7 +235,7 @@ Use the new name of the library in your sbt dependencies: `com.github.rameloni::
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| Release | Chisel fork version (from `rameloni/chisel`) | Firtool fork version (from `rameloni/circt`) | Tywaves-rs version | Surfer-tywaves version |
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|:-----------------------------------------------------------------------------------------------|:---------------------------------------------------------------------------------------------------|:---------------------------------------------------------------------------------|:------------------------------------------------------------------------------|:----------------------------------------------------------------------------------------------------------------------|
237-
| [0.4.0-SNAPSHOT]() _coming soon_ | [v6.4.3-tywaves-SNAPSHOT]() _coming soon_ | [v0.1.3](https://github.com/rameloni/circt/releases/tag/v0.1.3-tywaves-SNAPSHOT) | [v0.1.4](https://github.com/rameloni/tywaves-rs/releases/tag/v0.1.4-SNAPSHOT) | [v0.3.2-tywaves-dev-SNAPSHOT](https://gitlab.com/rameloni/surfer-tywaves-demo/-/releases/v0.3.2-tywaves-SNAPSHOT) |
238+
| [0.4.0-SNAPSHOT]() | [v6.4.3-tywaves-SNAPSHOT](https://github.com/rameloni/chisel/releases/tag/v6.4.3-tywaves-SNAPSHOT) | [v0.1.3](https://github.com/rameloni/circt/releases/tag/v0.1.3-tywaves-SNAPSHOT) | [v0.1.4](https://github.com/rameloni/tywaves-rs/releases/tag/v0.1.4-SNAPSHOT) | [v0.3.2-tywaves-dev-SNAPSHOT](https://gitlab.com/rameloni/surfer-tywaves-demo/-/releases/v0.3.2-tywaves-SNAPSHOT) |
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| [0.3.0-SNAPSHOT](https://github.com/rameloni/tywaves-chisel-demo/releases/tag/v0.3.0-SNAPSHOT) | [v6.4.2-tywaves-SNAPSHOT](https://github.com/rameloni/chisel/releases/tag/v6.4.2-tywaves-SNAPSHOT) | [v0.1.1](https://github.com/rameloni/circt/releases/tag/v0.1.1-tywaves-SNAPSHOT) | [v0.1.1](https://github.com/rameloni/tywaves-rs/releases/tag/v0.1.1-SNAPSHOT) | [v0.3.0-tywaves-dev-SNAPSHOT](https://gitlab.com/rameloni/surfer-tywaves-demo/-/releases/v0.3.0-tywaves-dev-SNAPSHOT) |
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## Old backend implementations ([ref](https://github.com/rameloni/tywaves-chisel-demo/wiki/An-alternative-solution-(old-demo-version)))

‎build.sbt

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,19 @@
1-
val chiselVersion = "6.4.2-tywaves-SNAPSHOT" // Local version of chisel
1+
val chiselVersion = "6.4.3-tywaves-SNAPSHOT" // Local version of chisel
22
val scalatestVersion = "3.2.16"
33
val circeVersion = "0.14.6"
44

55
val firtoolVersion = "0.1.3"
66
val firtoolFullName = "firtool-type-dbg-info-" ++ firtoolVersion
77

8-
val surferTywavesVersion = "0.3.2-dev"
8+
val surferTywavesVersion = "0.3.2"
99
val surferTywavesFullName = "surfer-tywaves-" ++ surferTywavesVersion
1010

1111
Compile / scalaSource := baseDirectory.value / "src/main/scala"
1212

1313
Test / scalaSource := baseDirectory.value / "src/test/scala"
1414

1515
ThisBuild / organization := "com.github.rameloni"
16-
ThisBuild / version := "0.4.0-SNAPSHOT-dev"
16+
ThisBuild / version := "0.4.0-SNAPSHOT"
1717
ThisBuild / scalaVersion := "2.13.14"
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1919
enablePlugins(ScalafmtPlugin)

‎example/.gitignore

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
*.vcd
2+
*.sv
3+
*.v
4+
*.fir
5+
*.mlir

‎example/gcd.test.scala

Lines changed: 33 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
//> using scala "2.13.14"
2-
//> using dep "com.github.rameloni::tywaves-chisel-api:0.3.0-SNAPSHOT"
2+
//> using dep "com.github.rameloni::tywaves-chisel-api:0.4.0-SNAPSHOT"
33
//> using dep "org.chipsalliance::chisel:6.4.0"
44
//> using plugin "org.chipsalliance:::chisel-plugin:6.4.0"
55
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"
@@ -10,8 +10,7 @@ import tywaves.simulator._
1010
import tywaves.simulator.ParametricSimulator._
1111
import tywaves.simulator.simulatorSettings._
1212
import chisel3._
13-
14-
13+
import circt.stage.ChiselStage
1514
// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._
1615
//import _root_.circt.stage.ChiselStage
1716
import org.scalatest.funspec.AnyFunSpec
@@ -30,7 +29,16 @@ class GCD extends Module {
3029
val x = Reg(UInt(32.W))
3130
val y = Reg(UInt(32.W))
3231

33-
when(x > y)(x := x -% y).otherwise(y := y -% x)
32+
val tmp = x + y
33+
when(x > y) {
34+
val myTmpVal: UInt = x -% y
35+
x := myTmpVal
36+
}.otherwise {
37+
val myTmpVal = y -% x
38+
val myTmpVal3 = Wire(UInt(32.W))
39+
myTmpVal3 := myTmpVal
40+
y := y -% x
41+
}
3442

3543
when(io.loadValues) { x := io.a; y := io.b }
3644

@@ -41,6 +49,17 @@ class GCD extends Module {
4149
class GCDTest extends AnyFunSpec with Matchers {
4250
describe("ParametricSimulator") {
4351
it("runs GCD correctly") {
52+
53+
val chiselStage = new ChiselStage(true)
54+
chiselStage.execute(
55+
args = Array("--target", "chirrtl"),
56+
annotations = Seq(
57+
chisel3.stage.ChiselGeneratorAnnotation(() => new GCD()),
58+
circt.stage.FirtoolOption("-g"),
59+
circt.stage.FirtoolOption("--emit-hgldd"),
60+
),
61+
)
62+
println("Hello, world!")
4463
simulate(new GCD(), Seq(VcdTrace, SaveWorkdirFile("gcdWorkdir"))) { gcd =>
4564
gcd.io.a.poke(24.U)
4665
gcd.io.b.poke(36.U)
@@ -68,6 +87,16 @@ class GCDTest extends AnyFunSpec with Matchers {
6887
gcd.clock.stepUntil(sentinelPort = gcd.io.resultIsValid, sentinelValue = 1, maxCycles = 10)
6988
gcd.io.resultIsValid.expect(true.B)
7089
gcd.io.result.expect(12)
90+
gcd.io.a.poke(24.U)
91+
gcd.io.b.poke(72.U)
92+
gcd.reset.poke(true.B)
93+
gcd.io.loadValues.poke(1.B)
94+
gcd.clock.step()
95+
gcd.io.loadValues.poke(0.B)
96+
gcd.reset.poke(false.B)
97+
gcd.clock.stepUntil(sentinelPort = gcd.io.resultIsValid, sentinelValue = 1, maxCycles = 10)
98+
gcd.io.resultIsValid.expect(true.B)
99+
gcd.io.result.expect(24)
71100
}
72101
}
73102
}

‎example/myfsm.test.scala

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,91 @@
1+
//> using scala "2.13.14"
2+
//> using dep "com.github.rameloni::tywaves-chisel-api:0.4.0-SNAPSHOT"
3+
//> using dep "org.chipsalliance::chisel:6.4.0"
4+
//> using plugin "org.chipsalliance:::chisel-plugin:6.4.0"
5+
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"
6+
//> using dep "org.scalatest::scalatest:3.2.18"
7+
8+
// DO NOT EDIT THE ORTHER OF THESE IMPORTS (it will be solved in future versions)
9+
import tywaves.simulator._
10+
import tywaves.simulator.simulatorSettings._
11+
import chisel3._
12+
// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._
13+
//import _root_.circt.stage.ChiselStage
14+
import org.scalatest.funspec.AnyFunSpec
15+
import org.scalatest.matchers.should.Matchers
16+
import circt.stage.ChiselStage
17+
18+
// Enum of possible states
19+
object MyFSMStates extends ChiselEnum {
20+
val IDLE, StateA, StateB, END = Value
21+
}
22+
23+
class FSM extends Bundle {
24+
25+
val inputState = IO(Input(MyFSMStates()))
26+
val state = RegInit(MyFSMStates.IDLE)
27+
val stateNxt = WireInit(MyFSMStates.IDLE)
28+
29+
val endConst = WireInit(MyFSMStates.END)
30+
31+
when(state === MyFSMStates.IDLE) {
32+
stateNxt := MyFSMStates.StateA
33+
}.elsewhen(state === MyFSMStates.StateA) {
34+
stateNxt := MyFSMStates.StateB
35+
}.elsewhen(state === MyFSMStates.StateB) {
36+
stateNxt := MyFSMStates.END
37+
}.otherwise {
38+
stateNxt := MyFSMStates.IDLE
39+
}
40+
41+
when(inputState === MyFSMStates.END) {
42+
state := MyFSMStates.IDLE
43+
}.otherwise {
44+
state := stateNxt
45+
}
46+
}
47+
48+
class MyFSM extends Module {
49+
val fsm = new FSM
50+
51+
val io = IO(new Bundle {
52+
val inputState = Input(MyFSMStates())
53+
})
54+
55+
val aConstBundle = Wire(new Bundle {
56+
val bit = Bool()
57+
val bv = UInt(32.W)
58+
val subbundle = new Bundle {
59+
val x = SInt(3.W)
60+
}
61+
})
62+
aConstBundle.bit := 1.B
63+
aConstBundle.bv := 34.U
64+
aConstBundle.subbundle.x := 2.S
65+
}
66+
67+
68+
class MyFSMTest extends AnyFunSpec with Matchers {
69+
70+
describe("TywavesSimulator") {
71+
it("runs MyFSM correctly") {
72+
import TywavesSimulator._
73+
val chiselStage = new ChiselStage(true)
74+
75+
chiselStage.execute(
76+
args = Array("--target", "chirrtl"),
77+
annotations = Seq(
78+
chisel3.stage.ChiselGeneratorAnnotation(() => new MyFSM()),
79+
circt.stage.FirtoolOption("-g"),
80+
circt.stage.FirtoolOption("--emit-hgldd"),
81+
),
82+
)
83+
simulate(new MyFSM(), Seq(VcdTrace, WithTywavesWaveforms(true)), simName = "runs_MYFSM_correctly_launch_tywaves") {
84+
fsm =>
85+
fsm.clock.step(10)
86+
fsm.clock.step(10)
87+
}
88+
}
89+
}
90+
91+
}

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