Merge pull request #387 from kurtjd/arch-width-fix

Make ARCH_WIDTH byte aligned instead of bit aligned

Author: romancardenas

riscv-rt/CHANGELOG.md

@@ -7,6 +7,12 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## v0.17.1 - 2026-01-13
+
+### Fixed
+
+- Fix `build.rs` so `ARCH_WIDTH` is passed to linker script in size of bytes (instead of bits)
+
 ## v0.17.0 - 2025-12-19
 
 ### Added

riscv-rt/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "riscv-rt"
-version = "0.17.0"
+version = "0.17.1"
 rust-version = "1.81"
 repository = "https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]

riscv-rt/build.rs

@@ -56,7 +56,8 @@ fn main() {
     let cargo_flags = env::var("CARGO_ENCODED_RUSTFLAGS").unwrap();
 
     if let Ok(target) = RiscvTarget::build(&target, &cargo_flags) {
-        let width = target.width();
+        // Linker script expects ARCH_WIDTH in bytes
+        let width_bytes = u32::from(target.width()) / 8;
 
         // set environment variable RISCV_RT_BASE_ISA to the base ISA of the target.
         println!(
@@ -86,6 +87,6 @@ fn main() {
                 println!("cargo:rustc-cfg={flag}");
             }
         }
-        add_linker_script(width.into()).unwrap();
+        add_linker_script(width_bytes).unwrap();
     }
 }