From a97a20116dd89ed4ab8132d1a2dfb0dfca0fd502 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas=20Rodr=C3=ADguez?= Date: Fri, 13 Jun 2025 22:15:26 +0200 Subject: [PATCH 01/10] Adapt riscv-semihosting to edition 2024 --- .github/workflows/riscv-semihosting.yaml | 4 ++-- riscv-semihosting/CHANGELOG.md | 4 ++++ riscv-semihosting/Cargo.toml | 6 +++--- riscv-semihosting/README.md | 6 +++--- riscv-semihosting/src/lib.rs | 14 ++++++++------ 5 files changed, 20 insertions(+), 14 deletions(-) diff --git a/.github/workflows/riscv-semihosting.yaml b/.github/workflows/riscv-semihosting.yaml index 66e28158..4536532d 100644 --- a/.github/workflows/riscv-semihosting.yaml +++ b/.github/workflows/riscv-semihosting.yaml @@ -11,8 +11,8 @@ jobs: build-riscv: strategy: matrix: - # All generated code should be running on stable now, MRSV is 1.67.0 - toolchain: [ stable, nightly, 1.67.0 ] + # All generated code should be running on stable now, MRSV is 1.85.0 + toolchain: [ stable, nightly, 1.85.0 ] target: - riscv32i-unknown-none-elf - riscv32imc-unknown-none-elf diff --git a/riscv-semihosting/CHANGELOG.md b/riscv-semihosting/CHANGELOG.md index 2c587ff8..bd570e7a 100644 --- a/riscv-semihosting/CHANGELOG.md +++ b/riscv-semihosting/CHANGELOG.md @@ -5,6 +5,10 @@ This project adheres to [Semantic Versioning](http://semver.org/). ## [Unreleased] +### Changed + +- Update to Rust edition 2024 (MSRV 1.85) + ## [v0.2.0] - 2025-06-10 ### Changed diff --git a/riscv-semihosting/Cargo.toml b/riscv-semihosting/Cargo.toml index 845812ec..91ac5dba 100644 --- a/riscv-semihosting/Cargo.toml +++ b/riscv-semihosting/Cargo.toml @@ -4,7 +4,7 @@ authors = [ "Jorge Aparicio ", "The RISC-V Team ", ] -description = "Semihosting for RISCV processors" +description = "Semihosting for RISC-V processors" documentation = "https://docs.rs/riscv-semihosting" keywords = ["semihosting", "riscv"] categories = ["no-std", "embedded"] @@ -13,8 +13,8 @@ name = "riscv-semihosting" readme = "README.md" repository = "https://github.com/riscv-rust/riscv" version = "0.2.0" -edition = "2021" -rust-version = "1.67" +edition = "2024" +rust-version = "1.85" [features] u-mode = [] diff --git a/riscv-semihosting/README.md b/riscv-semihosting/README.md index 56e89eb6..915df6e0 100644 --- a/riscv-semihosting/README.md +++ b/riscv-semihosting/README.md @@ -35,12 +35,12 @@ While `riscv-semihosting` is a good starting point for developing semihosted app # Minimum Supported Rust Version (MSRV) -This crate is guaranteed to compile on stable Rust 1.60.0 and up. It **won't** +This crate is guaranteed to compile on stable Rust 1.85.0 and up. It **won't** compile with older versions. ## License -Copyright 2018-2023 [RISC-V team][team] +Copyright 2018-2025 [RISC-V team][team] Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice @@ -69,4 +69,4 @@ to intervene to uphold that code of conduct. [CoC]: ../CODE_OF_CONDUCT.md [team]: https://github.com/rust-embedded/wg#the-risc-v-team [`semihosting`]: https://crates.io/crates/semihosting -[`cortex-m-semihosting`]: https://docs.rs/cortex-m-semihosting \ No newline at end of file +[`cortex-m-semihosting`]: https://docs.rs/cortex-m-semihosting diff --git a/riscv-semihosting/src/lib.rs b/riscv-semihosting/src/lib.rs index c7c1968f..152a80bb 100644 --- a/riscv-semihosting/src/lib.rs +++ b/riscv-semihosting/src/lib.rs @@ -202,7 +202,7 @@ pub mod nr; /// [semihosting operation]: https://developer.arm.com/documentation/dui0471/i/semihosting/semihosting-operations?lang=en #[inline(always)] pub unsafe fn syscall(nr: usize, arg: &T) -> usize { - syscall1(nr, arg as *const T as usize) + unsafe { syscall1(nr, arg as *const T as usize) } } /// Performs a semihosting operation, takes one integer as an argument @@ -221,7 +221,8 @@ pub unsafe fn syscall1(_nr: usize, _arg: usize) -> usize { // it will be treated as a regular break, hence the norvc option. // // See https://github.com/riscv/riscv-semihosting-spec for more details. - asm!(" + unsafe { + asm!(" .balign 16 .option push .option norvc @@ -230,10 +231,11 @@ pub unsafe fn syscall1(_nr: usize, _arg: usize) -> usize { srai x0, x0, 0x7 .option pop ", - inout("a0") nr, - inout("a1") arg => _, - options(nostack, preserves_flags), - ); + inout("a0") nr, + inout("a1") arg => _, + options(nostack, preserves_flags), + ) + }; nr } #[cfg(all(riscv, feature = "no-semihosting"))] From 211232510b35a4dec0ae4021781065c1fb86b092 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas=20Rodr=C3=ADguez?= Date: Sat, 14 Jun 2025 13:28:42 +0200 Subject: [PATCH 02/10] Adapt riscv-target-parser to edition 2024 --- .github/workflows/riscv-target-parser.yaml | 2 +- riscv-target-parser/CHANGELOG.md | 4 ++++ riscv-target-parser/Cargo.toml | 4 ++-- riscv-target-parser/README.md | 2 +- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/.github/workflows/riscv-target-parser.yaml b/.github/workflows/riscv-target-parser.yaml index fce646a2..a9151fc3 100644 --- a/.github/workflows/riscv-target-parser.yaml +++ b/.github/workflows/riscv-target-parser.yaml @@ -11,7 +11,7 @@ jobs: strategy: matrix: os: [ macos-latest, ubuntu-latest, windows-latest ] - toolchain: [ stable, nightly, 1.67.0 ] + toolchain: [ stable, nightly, 1.85.0 ] include: # Nightly is only for reference and allowed to fail - rust: nightly diff --git a/riscv-target-parser/CHANGELOG.md b/riscv-target-parser/CHANGELOG.md index b805fb6e..b2d762c5 100644 --- a/riscv-target-parser/CHANGELOG.md +++ b/riscv-target-parser/CHANGELOG.md @@ -5,6 +5,10 @@ This project adheres to [Semantic Versioning](http://semver.org/). ## [Unreleased] +### Changed + +- Update to Rust edition 2024 (MSRV 1.85) + ## [v0.1.2] - 2025-06-10 ### Fixed diff --git a/riscv-target-parser/Cargo.toml b/riscv-target-parser/Cargo.toml index 7612e387..ac8574c1 100644 --- a/riscv-target-parser/Cargo.toml +++ b/riscv-target-parser/Cargo.toml @@ -1,7 +1,7 @@ [package] name = "riscv-target-parser" version = "0.1.2" -rust-version = "1.61" +rust-version = "1.85" repository = "https://github.com/rust-embedded/riscv" authors = ["The RISC-V Team "] categories = ["embedded", "no-std"] @@ -9,4 +9,4 @@ description = "Parser for RISC-V target specifications" documentation = "https://docs.rs/riscv-target-parser" keywords = ["riscv", "build"] license = "ISC" -edition = "2021" +edition = "2024" diff --git a/riscv-target-parser/README.md b/riscv-target-parser/README.md index 0e8a8f04..50fa335d 100644 --- a/riscv-target-parser/README.md +++ b/riscv-target-parser/README.md @@ -11,7 +11,7 @@ This project is developed and maintained by the [RISC-V team][team]. ## Minimum Supported Rust Version (MSRV) -This crate is guaranteed to compile on stable Rust 1.61 and up. It *might* +This crate is guaranteed to compile on stable Rust 1.85 and up. It **won't** compile with older versions but that may change in any new patch release. ## License From 5b94358aa498271526b72dd799a43e562107d9db Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas=20Rodr=C3=ADguez?= Date: Mon, 16 Jun 2025 12:41:56 +0200 Subject: [PATCH 03/10] Adapt riscv-peripheral to edition 2024 --- .github/workflows/riscv-peripheral.yaml | 4 ++-- riscv-peripheral/CHANGELOG.md | 4 ++++ riscv-peripheral/Cargo.toml | 4 ++-- riscv-peripheral/README.md | 2 +- riscv-peripheral/src/aclint.rs | 6 ++++-- riscv-peripheral/src/aclint/mswi.rs | 2 +- riscv-peripheral/src/aclint/mtimer.rs | 2 +- riscv-peripheral/src/aclint/sswi.rs | 2 +- riscv-peripheral/src/common.rs | 2 +- riscv-peripheral/src/plic.rs | 2 +- riscv-peripheral/src/plic/enables.rs | 6 +++--- 11 files changed, 21 insertions(+), 15 deletions(-) diff --git a/.github/workflows/riscv-peripheral.yaml b/.github/workflows/riscv-peripheral.yaml index 571e383f..acf0da21 100644 --- a/.github/workflows/riscv-peripheral.yaml +++ b/.github/workflows/riscv-peripheral.yaml @@ -11,8 +11,8 @@ jobs: build-riscv: strategy: matrix: - # All generated code should be running on stable now, MRSV is 1.75.0 - toolchain: [ stable, nightly, 1.75.0 ] + # All generated code should be running on stable now, MRSV is 1.85.0 + toolchain: [ stable, nightly, 1.85.0 ] target: - riscv32i-unknown-none-elf - riscv32imc-unknown-none-elf diff --git a/riscv-peripheral/CHANGELOG.md b/riscv-peripheral/CHANGELOG.md index 91d4b45a..a06c80f9 100644 --- a/riscv-peripheral/CHANGELOG.md +++ b/riscv-peripheral/CHANGELOG.md @@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ## [Unreleased] +### Changed + +- Update to Rust edition 2024 (MSRV 1.85) + ## [v0.3.0] - 2025-06-10 ### Changed diff --git a/riscv-peripheral/Cargo.toml b/riscv-peripheral/Cargo.toml index 27b6b6b6..6a9a8eef 100644 --- a/riscv-peripheral/Cargo.toml +++ b/riscv-peripheral/Cargo.toml @@ -1,8 +1,8 @@ [package] name = "riscv-peripheral" version = "0.3.0" -edition = "2021" -rust-version = "1.75" +edition = "2024" +rust-version = "1.85" repository = "https://github.com/rust-embedded/riscv" authors = ["The RISC-V Team "] categories = ["embedded", "hardware-support", "no-std"] diff --git a/riscv-peripheral/README.md b/riscv-peripheral/README.md index 940f4bef..f9b7b26d 100644 --- a/riscv-peripheral/README.md +++ b/riscv-peripheral/README.md @@ -11,7 +11,7 @@ This project is developed and maintained by the [RISC-V team][team]. ## Minimum Supported Rust Version (MSRV) -This crate is guaranteed to compile on stable Rust 1.75 and up. It *might* +This crate is guaranteed to compile on stable Rust 1.85 and up. It **won't** compile with older versions but that may change in any new patch release. ## License diff --git a/riscv-peripheral/src/aclint.rs b/riscv-peripheral/src/aclint.rs index cbfea295..761c5563 100644 --- a/riscv-peripheral/src/aclint.rs +++ b/riscv-peripheral/src/aclint.rs @@ -78,8 +78,10 @@ impl CLINT { /// Enabling the `CLINT` may break mask-based critical sections. #[inline] pub unsafe fn enable(self) { - self.mswi().enable(); - self.mtimer().enable(); + unsafe { + self.mswi().enable(); + self.mtimer().enable(); + } } /// Disables machine timer **AND** software interrupts to prevent the CLINT from triggering interrupts. diff --git a/riscv-peripheral/src/aclint/mswi.rs b/riscv-peripheral/src/aclint/mswi.rs index afedea3c..bd357c89 100644 --- a/riscv-peripheral/src/aclint/mswi.rs +++ b/riscv-peripheral/src/aclint/mswi.rs @@ -64,7 +64,7 @@ impl MSWI { /// Enabling interrupts may break mask-based critical sections. #[inline] pub unsafe fn enable(self) { - mie::set_msoft(); + unsafe { mie::set_msoft() }; } /// Disables machine software interrupts in the current HART. diff --git a/riscv-peripheral/src/aclint/mtimer.rs b/riscv-peripheral/src/aclint/mtimer.rs index 0e2fc834..66b3465e 100644 --- a/riscv-peripheral/src/aclint/mtimer.rs +++ b/riscv-peripheral/src/aclint/mtimer.rs @@ -81,7 +81,7 @@ impl MTIMER { /// Enabling interrupts may break mask-based critical sections. #[inline] pub unsafe fn enable(self) { - mie::set_mtimer(); + unsafe { mie::set_mtimer() }; } /// Disables machine timer interrupts in the current HART. diff --git a/riscv-peripheral/src/aclint/sswi.rs b/riscv-peripheral/src/aclint/sswi.rs index b6eed9d1..b3f68ab8 100644 --- a/riscv-peripheral/src/aclint/sswi.rs +++ b/riscv-peripheral/src/aclint/sswi.rs @@ -55,7 +55,7 @@ impl SSWI { /// Enabling interrupts may break mask-based critical sections. #[inline] pub unsafe fn enable(self) { - sie::set_ssoft(); + unsafe { sie::set_ssoft() }; } /// Disables supervisor software interrupts in the current HART. diff --git a/riscv-peripheral/src/common.rs b/riscv-peripheral/src/common.rs index ec327bc5..a22b6d5f 100644 --- a/riscv-peripheral/src/common.rs +++ b/riscv-peripheral/src/common.rs @@ -265,7 +265,7 @@ macro_rules! peripheral { #[inline] pub const unsafe fn new(address: usize) -> Self { Self { - register: $crate::common::Reg::new(address as _), + register: unsafe { $crate::common::Reg::new(address as _) }, } } } diff --git a/riscv-peripheral/src/plic.rs b/riscv-peripheral/src/plic.rs index 847c89a0..6d7c0125 100644 --- a/riscv-peripheral/src/plic.rs +++ b/riscv-peripheral/src/plic.rs @@ -72,7 +72,7 @@ impl PLIC

{ /// Enabling the `PLIC` may break mask-based critical sections. #[inline] pub unsafe fn enable(self) { - mie::set_mext(); + unsafe { mie::set_mext() }; } /// Disables machine external interrupts to prevent the PLIC from triggering interrupts. diff --git a/riscv-peripheral/src/plic/enables.rs b/riscv-peripheral/src/plic/enables.rs index 016eb863..1acccf26 100644 --- a/riscv-peripheral/src/plic/enables.rs +++ b/riscv-peripheral/src/plic/enables.rs @@ -1,6 +1,6 @@ //! Interrupt enables register of a PLIC context. -use crate::common::{Reg, RW}; +use crate::common::{RW, Reg}; use riscv_pac::ExternalInterruptNumber; /// Enables register of a PLIC context. @@ -77,7 +77,7 @@ impl ENABLES { let offset = (source / u32::BITS as usize) as _; // SAFETY: valid interrupt number let reg: Reg = unsafe { Reg::new(self.ptr.offset(offset)) }; - reg.atomic_set_bit(source % u32::BITS as usize, order); + unsafe { reg.atomic_set_bit(source % u32::BITS as usize, order) }; } /// Disables an interrupt source for the PLIC context. @@ -115,7 +115,7 @@ impl ENABLES { let offset = (source / u32::BITS as usize) as _; // SAFETY: valid interrupt number let reg: Reg = unsafe { Reg::new(self.ptr.offset(offset)) }; - reg.atomic_clear_bit(source % u32::BITS as usize, order); + unsafe { reg.atomic_clear_bit(source % u32::BITS as usize, order) }; } /// Enables all the external interrupt sources for the PLIC context. From fd2d96c7c6a8f977763f53b6fd849e17dc9a6060 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas=20Rodr=C3=ADguez?= Date: Mon, 16 Jun 2025 12:46:21 +0200 Subject: [PATCH 04/10] Fix formatting in riscv-peripheral --- riscv-peripheral/src/hal/aclint.rs | 2 +- riscv-peripheral/src/plic/pendings.rs | 2 +- riscv-peripheral/src/plic/priorities.rs | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/riscv-peripheral/src/hal/aclint.rs b/riscv-peripheral/src/hal/aclint.rs index 296decf1..7bc891f8 100644 --- a/riscv-peripheral/src/hal/aclint.rs +++ b/riscv-peripheral/src/hal/aclint.rs @@ -1,6 +1,6 @@ //! Delay trait implementation for (A)CLINT peripherals -use crate::aclint::mtimer::{Mtimer, MTIMER}; +use crate::aclint::mtimer::{MTIMER, Mtimer}; use crate::hal::delay::DelayNs; impl DelayNs for MTIMER { diff --git a/riscv-peripheral/src/plic/pendings.rs b/riscv-peripheral/src/plic/pendings.rs index 12b170ce..bb19ba2c 100644 --- a/riscv-peripheral/src/plic/pendings.rs +++ b/riscv-peripheral/src/plic/pendings.rs @@ -1,6 +1,6 @@ //! Interrupt pending bits register. -use crate::common::{Reg, RO}; +use crate::common::{RO, Reg}; use riscv_pac::ExternalInterruptNumber; /// Interrupts pending bits register. diff --git a/riscv-peripheral/src/plic/priorities.rs b/riscv-peripheral/src/plic/priorities.rs index 725cd6d9..f30b1c27 100644 --- a/riscv-peripheral/src/plic/priorities.rs +++ b/riscv-peripheral/src/plic/priorities.rs @@ -1,6 +1,6 @@ //! Interrupts Priorities register. -use crate::common::{Reg, RW}; +use crate::common::{RW, Reg}; use riscv_pac::{ExternalInterruptNumber, PriorityNumber}; /// Interrupts priorities register. From 3f0db98416bb76a70f23a9d87514a4c7a093e794 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas=20Rodr=C3=ADguez?= Date: Mon, 16 Jun 2025 15:44:02 +0200 Subject: [PATCH 05/10] Adapt riscv-pac to edition 2024 --- riscv-pac/CHANGELOG.md | 4 ++++ riscv-pac/Cargo.toml | 4 ++-- riscv-pac/README.md | 2 +- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/riscv-pac/CHANGELOG.md b/riscv-pac/CHANGELOG.md index 9dcfcd6a..242ea7c4 100644 --- a/riscv-pac/CHANGELOG.md +++ b/riscv-pac/CHANGELOG.md @@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ## [Unreleased] +### Changed + +- Update to Rust edition 2024 (MSRV 1.85) + ## [v0.2.0] - 2024-10-19 ### Added diff --git a/riscv-pac/Cargo.toml b/riscv-pac/Cargo.toml index b5ba86b2..afc588fe 100644 --- a/riscv-pac/Cargo.toml +++ b/riscv-pac/Cargo.toml @@ -1,8 +1,8 @@ [package] name = "riscv-pac" version = "0.2.0" -edition = "2021" -rust-version = "1.60" +edition = "2024" +rust-version = "1.85" repository = "https://github.com/rust-embedded/riscv" authors = ["The RISC-V Team "] categories = ["embedded", "hardware-support", "no-std"] diff --git a/riscv-pac/README.md b/riscv-pac/README.md index fada9925..8b59f370 100644 --- a/riscv-pac/README.md +++ b/riscv-pac/README.md @@ -11,7 +11,7 @@ This project is developed and maintained by the [RISC-V team][team]. ## Minimum Supported Rust Version (MSRV) -This crate is guaranteed to compile on stable Rust 1.60 and up. It *might* +This crate is guaranteed to compile on stable Rust 1.85 and up. It **won't** compile with older versions but that may change in any new patch release. ## License From 85b29362f33712d260a77388caaeffa2740bf481 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas=20Rodr=C3=ADguez?= Date: Mon, 16 Jun 2025 15:46:23 +0200 Subject: [PATCH 06/10] Adapt riscv to edition 2024 --- .github/workflows/riscv.yaml | 4 +- riscv/CHANGELOG.md | 4 ++ riscv/Cargo.toml | 4 +- riscv/README.md | 2 +- riscv/macros/Cargo.toml | 2 +- riscv/macros/src/lib.rs | 16 ++++---- riscv/src/asm.rs | 2 +- riscv/src/critical_section.rs | 2 +- riscv/src/interrupt/machine.rs | 14 ++++--- riscv/src/interrupt/supervisor.rs | 14 ++++--- riscv/src/register/cycle.rs | 2 +- riscv/src/register/hpmcounterx.rs | 2 +- riscv/src/register/instret.rs | 2 +- riscv/src/register/macros.rs | 60 +++++++++++++++-------------- riscv/src/register/mcounteren.rs | 8 ++-- riscv/src/register/mcountinhibit.rs | 8 ++-- riscv/src/register/mcycle.rs | 2 +- riscv/src/register/mhpmcounterx.rs | 2 +- riscv/src/register/minstret.rs | 2 +- riscv/src/register/mstatus.rs | 32 +++++++-------- riscv/src/register/mstatush.rs | 8 ++-- riscv/src/register/satp.rs | 8 ++-- riscv/src/register/scause.rs | 2 +- riscv/src/register/scounteren.rs | 8 ++-- riscv/src/register/sstatus.rs | 8 ++-- riscv/src/register/stval.rs | 2 +- riscv/src/register/time.rs | 2 +- 27 files changed, 116 insertions(+), 106 deletions(-) diff --git a/.github/workflows/riscv.yaml b/.github/workflows/riscv.yaml index cf8a1e94..c80f27f2 100644 --- a/.github/workflows/riscv.yaml +++ b/.github/workflows/riscv.yaml @@ -11,8 +11,8 @@ jobs: build-riscv: strategy: matrix: - # All generated code should be running on stable now, MRSV is 1.67.0 - toolchain: [ stable, nightly, 1.67.0 ] + # All generated code should be running on stable now, MRSV is 1.85.0 + toolchain: [ stable, nightly, 1.85.0 ] target: - riscv32i-unknown-none-elf - riscv32imc-unknown-none-elf diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md index 768d9ab0..5832f155 100644 --- a/riscv/CHANGELOG.md +++ b/riscv/CHANGELOG.md @@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ## [Unreleased] +### Changed + +- Update to Rust edition 2024 (MSRV 1.85) + ## [v0.14.0] - 2025-06-10 ### Added diff --git a/riscv/Cargo.toml b/riscv/Cargo.toml index db32ab6d..9f13e130 100644 --- a/riscv/Cargo.toml +++ b/riscv/Cargo.toml @@ -1,8 +1,8 @@ [package] name = "riscv" version = "0.14.0" -edition = "2021" -rust-version = "1.67" +edition = "2024" +rust-version = "1.85" repository = "https://github.com/rust-embedded/riscv" authors = ["The RISC-V Team "] categories = ["embedded", "hardware-support", "no-std"] diff --git a/riscv/README.md b/riscv/README.md index 2a958981..04b73928 100644 --- a/riscv/README.md +++ b/riscv/README.md @@ -11,7 +11,7 @@ This project is developed and maintained by the [RISC-V team][team]. ## Minimum Supported Rust Version (MSRV) -This crate is guaranteed to compile on stable Rust 1.61 and up. It *might* +This crate is guaranteed to compile on stable Rust 1.85 and up. It **won't** compile with older versions but that may change in any new patch release. ## License diff --git a/riscv/macros/Cargo.toml b/riscv/macros/Cargo.toml index 6b940d6b..755496c1 100644 --- a/riscv/macros/Cargo.toml +++ b/riscv/macros/Cargo.toml @@ -10,7 +10,7 @@ license = "MIT OR Apache-2.0" name = "riscv-macros" repository = "https://github.com/rust-embedded/riscv" version = "0.2.0" -edition = "2021" +edition = "2024" [lib] proc-macro = true diff --git a/riscv/macros/src/lib.rs b/riscv/macros/src/lib.rs index c03f3c43..47c2b4d5 100644 --- a/riscv/macros/src/lib.rs +++ b/riscv/macros/src/lib.rs @@ -4,10 +4,10 @@ use quote::quote; use std::collections::HashMap; use std::str::FromStr; use syn::{ + Data, DeriveInput, Ident, Token, parse::{Parse, ParseStream}, parse_macro_input, spanned::Spanned, - Data, DeriveInput, Ident, Token, }; /// Struct to represent a function parameter. @@ -275,7 +275,7 @@ impl PacEnumItem { _ => { return quote!(compile_error!( "RISCV_MTVEC_ALIGN is not a power of 2 (minimum 4)" - )) + )); } }; let mut asm = format!( @@ -373,28 +373,28 @@ core::arch::global_asm!(" // Push the interrupt handler functions and the interrupt array res.push(quote! { #cfg_v_trap - extern "C" { + unsafe extern "C" { #(#handlers;)* } #cfg_v_trap #[doc(hidden)] - #[no_mangle] + #[unsafe(no_mangle)] pub static #vector_table: [Option; #max_discriminant + 1] = [ #(#interrupt_array),* ]; #cfg_v_trap #[inline] - #[no_mangle] + #[unsafe(no_mangle)] unsafe extern "C" fn #dispatch_fn_name(#(#dispatch_fn_args),*) { - extern "C" { + unsafe extern "C" { fn #default_handler(#(#extern_signature),*); } match #vector_table.get(code) { - Some(Some(handler)) => handler(#(#handler_input),*), - _ => #default_handler(#(#handler_input),*), + Some(Some(handler)) => unsafe { handler(#(#handler_input),*) }, + _ => unsafe { #default_handler(#(#handler_input),*) }, } } }); diff --git a/riscv/src/asm.rs b/riscv/src/asm.rs index 5e471ff1..48d4191e 100644 --- a/riscv/src/asm.rs +++ b/riscv/src/asm.rs @@ -6,7 +6,7 @@ macro_rules! instruction { #[inline(always)] pub unsafe fn $fnname() { #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] - core::arch::asm!($asm, $($options)*); + unsafe { core::arch::asm!($asm, $($options)*) }; #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))] unimplemented!(); } diff --git a/riscv/src/critical_section.rs b/riscv/src/critical_section.rs index 908daec7..77add43e 100644 --- a/riscv/src/critical_section.rs +++ b/riscv/src/critical_section.rs @@ -1,4 +1,4 @@ -use critical_section::{set_impl, Impl, RawRestoreState}; +use critical_section::{Impl, RawRestoreState, set_impl}; use crate::interrupt; diff --git a/riscv/src/interrupt/machine.rs b/riscv/src/interrupt/machine.rs index d88ceb46..bc0cc362 100644 --- a/riscv/src/interrupt/machine.rs +++ b/riscv/src/interrupt/machine.rs @@ -3,8 +3,8 @@ use crate::{ register::{mcause, mepc, mstatus}, }; use riscv_pac::{ - result::{Error, Result}, CoreInterruptNumber, ExceptionNumber, InterruptNumber, + result::{Error, Result}, }; /// Standard M-mode RISC-V interrupts @@ -110,7 +110,7 @@ pub fn disable() { /// Do not call this function inside a critical section. #[inline] pub unsafe fn enable() { - mstatus::set_mie() + unsafe { mstatus::set_mie() } } /// Retrieves the cause of a trap in the current hart (machine mode). @@ -181,7 +181,7 @@ where let mepc = mepc::read(); // enable interrupts to allow nested interrupts - enable(); + unsafe { enable() }; let r = f(); @@ -193,10 +193,12 @@ where // Restore MSTATUS.PIE, MSTATUS.MPP, and SEPC if mstatus.mpie() { - mstatus::set_mpie(); + unsafe { mstatus::set_mpie() }; } - mstatus::set_mpp(mstatus.mpp()); - mepc::write(mepc); + unsafe { + mstatus::set_mpp(mstatus.mpp()); + mepc::write(mepc); + }; r } diff --git a/riscv/src/interrupt/supervisor.rs b/riscv/src/interrupt/supervisor.rs index ddb913c2..25c5c958 100644 --- a/riscv/src/interrupt/supervisor.rs +++ b/riscv/src/interrupt/supervisor.rs @@ -3,8 +3,8 @@ use crate::{ register::{scause, sepc, sstatus}, }; use riscv_pac::{ - result::{Error, Result}, CoreInterruptNumber, ExceptionNumber, InterruptNumber, + result::{Error, Result}, }; /// Interrupt @@ -102,7 +102,7 @@ pub fn disable() { /// Do not call this function inside a critical section. #[inline] pub unsafe fn enable() { - sstatus::set_sie() + unsafe { sstatus::set_sie() } } /// Retrieves the cause of a trap in the current hart (supervisor mode). @@ -173,7 +173,7 @@ where let sepc = sepc::read(); // enable interrupts to allow nested interrupts - enable(); + unsafe { enable() }; let r = f(); @@ -185,10 +185,12 @@ where // Restore SSTATUS.SPIE, SSTATUS.SPP, and SEPC if sstatus.spie() { - sstatus::set_spie(); + unsafe { sstatus::set_spie() }; + } + unsafe { + sstatus::set_spp(sstatus.spp()); + sepc::write(sepc); } - sstatus::set_spp(sstatus.spp()); - sepc::write(sepc); r } diff --git a/riscv/src/register/cycle.rs b/riscv/src/register/cycle.rs index 8499de3d..43210a7a 100644 --- a/riscv/src/register/cycle.rs +++ b/riscv/src/register/cycle.rs @@ -5,4 +5,4 @@ //! S-mode is implemented or not read_csr_as_usize!(0xC00); -read_composite_csr!(super::cycleh::read(), read()); +read_composite_csr!(super::cycleh::read, read); diff --git a/riscv/src/register/hpmcounterx.rs b/riscv/src/register/hpmcounterx.rs index 62fbc8a2..c6865848 100644 --- a/riscv/src/register/hpmcounterx.rs +++ b/riscv/src/register/hpmcounterx.rs @@ -5,7 +5,7 @@ macro_rules! reg { /// Performance-monitoring counter pub mod $csrl { read_csr_as_usize!($addr); - read_composite_csr!(super::$csrh::read(), read()); + read_composite_csr!(super::$csrh::read, read); } }; } diff --git a/riscv/src/register/instret.rs b/riscv/src/register/instret.rs index 95c0b518..005bb244 100644 --- a/riscv/src/register/instret.rs +++ b/riscv/src/register/instret.rs @@ -5,4 +5,4 @@ //! S-mode is implemented or not read_csr_as_usize!(0xC02); -read_composite_csr!(super::instreth::read(), read()); +read_composite_csr!(super::instreth::read, read); diff --git a/riscv/src/register/macros.rs b/riscv/src/register/macros.rs index c9b6254f..86becfd2 100644 --- a/riscv/src/register/macros.rs +++ b/riscv/src/register/macros.rs @@ -14,7 +14,7 @@ macro_rules! read_csr { /// **WARNING**: panics on non-`riscv` targets. #[inline(always)] unsafe fn _read() -> usize { - _try_read().unwrap() + unsafe { _try_read() }.unwrap() } /// Attempts to read the CSR. @@ -24,7 +24,7 @@ macro_rules! read_csr { #[cfg($($cfg),*)] () => { let r: usize; - core::arch::asm!(concat!("csrrs {0}, ", stringify!($csr_number), ", x0"), out(reg) r); + unsafe { core::arch::asm!(concat!("csrrs {0}, ", stringify!($csr_number), ", x0"), out(reg) r) }; Ok(r) } #[cfg(not($($cfg),*))] @@ -157,7 +157,7 @@ macro_rules! write_csr { /// **WARNING**: panics on non-`riscv` targets. #[inline(always)] unsafe fn _write(bits: usize) { - _try_write(bits).unwrap(); + unsafe { _try_write(bits) }.unwrap(); } /// Attempts to write the CSR. @@ -167,7 +167,7 @@ macro_rules! write_csr { match () { #[cfg($($cfg),*)] () => { - core::arch::asm!(concat!("csrrw x0, ", stringify!($csr_number), ", {0}"), in(reg) bits); + unsafe { core::arch::asm!(concat!("csrrw x0, ", stringify!($csr_number), ", {0}"), in(reg) bits) }; Ok(()) } #[cfg(not($($cfg),*))] @@ -206,13 +206,13 @@ macro_rules! write_csr_as { /// **WARNING**: panics on non-`riscv` targets. #[inline] pub unsafe fn write(value: $csr_type) { - _write(value.bits); + unsafe { _write(value.bits) }; } /// Attempts to write the CSR. #[inline] pub unsafe fn try_write(value: $csr_type) -> $crate::result::Result<()> { - _try_write(value.bits) + unsafe { _try_write(value.bits) } } }; (safe $csr_type:ty, $csr_number:literal, $($cfg:meta),*) => { @@ -262,13 +262,13 @@ macro_rules! write_csr_as_usize { /// **WARNING**: panics on non-`riscv` targets. #[inline] pub unsafe fn write(bits: usize) { - _write(bits); + unsafe { _write(bits) }; } /// Attempts to write the CSR. #[inline] pub unsafe fn try_write(bits: usize) -> $crate::result::Result<()> { - _try_write(bits) + unsafe { _try_write(bits) } } }; (safe $csr_number:literal, $($cfg:meta),*) => { @@ -315,7 +315,7 @@ macro_rules! set { /// **WARNING**: panics on non-`riscv` targets. #[inline(always)] unsafe fn _set(bits: usize) { - _try_set(bits).unwrap(); + unsafe { _try_set(bits) }.unwrap(); } /// Attempts to set the CSR. @@ -325,7 +325,7 @@ macro_rules! set { match () { #[cfg($($cfg),*)] () => { - core::arch::asm!(concat!("csrrs x0, ", stringify!($csr_number), ", {0}"), in(reg) bits); + unsafe { core::arch::asm!(concat!("csrrs x0, ", stringify!($csr_number), ", {0}"), in(reg) bits) }; Ok(()) } #[cfg(not($($cfg),*))] @@ -359,7 +359,7 @@ macro_rules! clear { /// **WARNING**: panics on non-`riscv` targets. #[inline(always)] unsafe fn _clear(bits: usize) { - _try_clear(bits).unwrap(); + unsafe { _try_clear(bits) } .unwrap(); } /// Attempts to clear the CSR. @@ -369,7 +369,7 @@ macro_rules! clear { match () { #[cfg($($cfg),*)] () => { - core::arch::asm!(concat!("csrrc x0, ", stringify!($csr_number), ", {0}"), in(reg) bits); + unsafe { core::arch::asm!(concat!("csrrc x0, ", stringify!($csr_number), ", {0}"), in(reg) bits) }; Ok(()) } #[cfg(not($($cfg),*))] @@ -396,7 +396,8 @@ macro_rules! set_csr { $(#[$attr])* #[inline] pub unsafe fn $set_field() { - _set($e); + let e = $e; + unsafe { _set(e) }; } }; } @@ -408,7 +409,8 @@ macro_rules! clear_csr { $(#[$attr])* #[inline] pub unsafe fn $clear_field() { - _clear($e); + let e = $e; + unsafe { _clear(e) }; } }; } @@ -428,22 +430,22 @@ macro_rules! set_clear_csr { /// - `RV64`: reads a 64-bit value from `lo` #[macro_export] macro_rules! read_composite_csr { - ($hi:expr, $lo:expr) => { + ($hi:path, $lo:path) => { /// Reads the CSR as a 64-bit value #[inline] pub fn read64() -> u64 { match () { #[cfg(target_arch = "riscv32")] () => loop { - let hi = $hi; - let lo = $lo; - if hi == $hi { + let hi = $hi(); + let lo = $lo(); + if hi == $hi() { return ((hi as u64) << 32) | lo as u64; } }, #[cfg(not(target_arch = "riscv32"))] - () => $lo as u64, + () => $lo() as u64, } } }; @@ -455,19 +457,19 @@ macro_rules! read_composite_csr { /// - `RV64`: writes a 64-bit value into `lo` #[macro_export] macro_rules! write_composite_csr { - ($hi:expr, $lo:expr) => { + ($hi:path, $lo:path) => { /// Writes the CSR as a 64-bit value #[inline] pub unsafe fn write64(bits: u64) { match () { #[cfg(target_arch = "riscv32")] () => { - $hi((bits >> 32) as usize); - $lo(bits as usize); + unsafe { $hi((bits >> 32) as usize) }; + unsafe { $lo(bits as usize) }; } #[cfg(not(target_arch = "riscv32"))] - () => $lo(bits as usize), + () => unsafe { $lo(bits as usize) }, } } }; @@ -480,7 +482,7 @@ macro_rules! set_pmp { /// **WARNING**: panics on non-`riscv` targets, and/or if `index` is out-of-bounds. #[inline] pub unsafe fn set_pmp(index: usize, range: Range, permission: Permission, locked: bool) { - try_set_pmp(index, range, permission, locked).unwrap() + unsafe { try_set_pmp(index, range, permission, locked) }.unwrap(); } /// Attempts to set the pmp configuration corresponding to the index. @@ -503,11 +505,11 @@ macro_rules! set_pmp { }?; if index < max { - let mut value = _try_read()?; + let mut value = unsafe { _try_read() }?; value &= !(0xFF << (8 * index)); // clear previous value let byte = (locked as usize) << 7 | (range as usize) << 3 | (permission as usize); value |= byte << (8 * index); - _try_write(value) + unsafe { _try_write(value) } } else { Err($crate::result::Error::IndexOutOfBounds { index, @@ -526,7 +528,7 @@ macro_rules! clear_pmp { /// **WARNING**: panics on non-`riscv` targets, and/or if `index` is out-of-bounds. #[inline] pub unsafe fn clear_pmp(index: usize) { - try_clear_pmp(index).unwrap(); + unsafe { try_clear_pmp(index) }.unwrap(); } /// Attempts to clear the pmp configuration corresponding to the index. @@ -544,9 +546,9 @@ macro_rules! clear_pmp { }?; if index < max { - let mut value = _try_read()?; + let mut value = unsafe { _try_read() }?; value &= !(0xFF << (8 * index)); // clear previous value - _try_write(value) + unsafe { _try_write(value) } } else { Err($crate::result::Error::IndexOutOfBounds { index, diff --git a/riscv/src/register/mcounteren.rs b/riscv/src/register/mcounteren.rs index 37d9854a..0df3948e 100644 --- a/riscv/src/register/mcounteren.rs +++ b/riscv/src/register/mcounteren.rs @@ -57,7 +57,7 @@ set_clear_csr!( /// - `index` out-of-bounds #[inline] pub unsafe fn set_hpm(index: usize) { - try_set_hpm(index).unwrap(); + unsafe { try_set_hpm(index) }.unwrap(); } /// Attempts to enable the "hpm\[X\]" counter. @@ -66,7 +66,7 @@ pub unsafe fn set_hpm(index: usize) { #[inline] pub unsafe fn try_set_hpm(index: usize) -> Result<()> { if (3..32).contains(&index) { - _try_set(1 << index) + unsafe { _try_set(1 << index) } } else { Err(Error::IndexOutOfBounds { index, @@ -86,7 +86,7 @@ pub unsafe fn try_set_hpm(index: usize) -> Result<()> { /// - `index` out-of-bounds #[inline] pub unsafe fn clear_hpm(index: usize) { - try_clear_hpm(index).unwrap(); + unsafe { try_clear_hpm(index) }.unwrap(); } /// Attempts to disable the "hpm\[X\]" counter. @@ -95,7 +95,7 @@ pub unsafe fn clear_hpm(index: usize) { #[inline] pub unsafe fn try_clear_hpm(index: usize) -> Result<()> { if (3..32).contains(&index) { - _try_clear(1 << index) + unsafe { _try_clear(1 << index) } } else { Err(Error::IndexOutOfBounds { index, diff --git a/riscv/src/register/mcountinhibit.rs b/riscv/src/register/mcountinhibit.rs index a3895124..dc9dc876 100644 --- a/riscv/src/register/mcountinhibit.rs +++ b/riscv/src/register/mcountinhibit.rs @@ -41,13 +41,13 @@ set_clear_csr!( #[inline] pub unsafe fn set_hpm(index: usize) { - try_set_hpm(index).unwrap(); + unsafe { try_set_hpm(index) }.unwrap(); } #[inline] pub unsafe fn try_set_hpm(index: usize) -> Result<()> { if (3..32).contains(&index) { - _try_set(1 << index) + unsafe { _try_set(1 << index) } } else { Err(Error::IndexOutOfBounds { index, @@ -59,13 +59,13 @@ pub unsafe fn try_set_hpm(index: usize) -> Result<()> { #[inline] pub unsafe fn clear_hpm(index: usize) { - try_clear_hpm(index).unwrap(); + unsafe { try_clear_hpm(index) }.unwrap(); } #[inline] pub unsafe fn try_clear_hpm(index: usize) -> Result<()> { if (3..32).contains(&index) { - _try_clear(1 << index) + unsafe { _try_clear(1 << index) } } else { Err(Error::IndexOutOfBounds { index, diff --git a/riscv/src/register/mcycle.rs b/riscv/src/register/mcycle.rs index 70c10f57..23e3c8ca 100644 --- a/riscv/src/register/mcycle.rs +++ b/riscv/src/register/mcycle.rs @@ -2,5 +2,5 @@ read_csr_as_usize!(0xB00); write_csr_as_usize!(0xB00); -read_composite_csr!(super::mcycleh::read(), read()); +read_composite_csr!(super::mcycleh::read, read); write_composite_csr!(super::mcycleh::write, write); diff --git a/riscv/src/register/mhpmcounterx.rs b/riscv/src/register/mhpmcounterx.rs index e4c1b01f..b859bbf9 100644 --- a/riscv/src/register/mhpmcounterx.rs +++ b/riscv/src/register/mhpmcounterx.rs @@ -6,7 +6,7 @@ macro_rules! reg { pub mod $csrl { read_csr_as_usize!($addr); write_csr_as_usize!($addr); - read_composite_csr!(super::$csrh::read(), read()); + read_composite_csr!(super::$csrh::read, read); } }; } diff --git a/riscv/src/register/minstret.rs b/riscv/src/register/minstret.rs index 46a4e6b2..98848693 100644 --- a/riscv/src/register/minstret.rs +++ b/riscv/src/register/minstret.rs @@ -2,5 +2,5 @@ read_csr_as_usize!(0xB02); write_csr_as_usize!(0xB02); -read_composite_csr!(super::minstreth::read(), read()); +read_composite_csr!(super::minstreth::read, read); write_composite_csr!(super::minstreth::write, write); diff --git a/riscv/src/register/mstatus.rs b/riscv/src/register/mstatus.rs index 0e3f4616..dcf71e85 100644 --- a/riscv/src/register/mstatus.rs +++ b/riscv/src/register/mstatus.rs @@ -389,8 +389,8 @@ set_clear_csr!( #[inline] pub unsafe fn set_ube(endianness: Endianness) { match endianness { - Endianness::BigEndian => _set(1 << 6), - Endianness::LittleEndian => _clear(1 << 6), + Endianness::BigEndian => unsafe { _set(1 << 6) }, + Endianness::LittleEndian => unsafe { _clear(1 << 6) }, } } @@ -398,36 +398,36 @@ pub unsafe fn set_ube(endianness: Endianness) { #[inline] pub unsafe fn set_spp(spp: SPP) { match spp { - SPP::Supervisor => _set(1 << 8), - SPP::User => _clear(1 << 8), + SPP::Supervisor => unsafe { _set(1 << 8) }, + SPP::User => unsafe { _clear(1 << 8) }, } } /// Machine Previous Privilege Mode #[inline] pub unsafe fn set_mpp(mpp: MPP) { - let mut value = _read(); + let mut value = unsafe { _read() }; value &= !(0x3 << 11); // clear previous value value |= (mpp as usize) << 11; - _write(value); + unsafe { _write(value) }; } /// Floating-point extension state #[inline] pub unsafe fn set_fs(fs: FS) { - let mut value = _read(); + let mut value = unsafe { _read() }; value &= !(0x3 << 13); // clear previous value value |= (fs as usize) << 13; - _write(value); + unsafe { _write(value) }; } /// Vector extension state #[inline] pub unsafe fn set_vs(vs: VS) { - let mut value = _read(); + let mut value = unsafe { _read() }; value &= !(0x3 << 9); // clear previous value value |= (vs as usize) << 9; - _write(value); + unsafe { _write(value) }; } /// Set S-mode non-instruction-fetch memory endianness @@ -439,11 +439,11 @@ pub unsafe fn set_vs(vs: VS) { pub unsafe fn set_sbe(endianness: Endianness) { match () { #[cfg(riscv32)] - () => super::mstatush::set_sbe(endianness), + () => unsafe { super::mstatush::set_sbe(endianness) }, #[cfg(not(riscv32))] () => match endianness { - Endianness::BigEndian => _set(1 << 36), - Endianness::LittleEndian => _clear(1 << 36), + Endianness::BigEndian => unsafe { _set(1 << 36) }, + Endianness::LittleEndian => unsafe { _clear(1 << 36) }, }, } } @@ -457,11 +457,11 @@ pub unsafe fn set_sbe(endianness: Endianness) { pub unsafe fn set_mbe(endianness: Endianness) { match () { #[cfg(riscv32)] - () => super::mstatush::set_mbe(endianness), + () => unsafe { super::mstatush::set_mbe(endianness) }, #[cfg(not(riscv32))] () => match endianness { - Endianness::BigEndian => _set(1 << 37), - Endianness::LittleEndian => _clear(1 << 37), + Endianness::BigEndian => unsafe { _set(1 << 37) }, + Endianness::LittleEndian => unsafe { _clear(1 << 37) }, }, } } diff --git a/riscv/src/register/mstatush.rs b/riscv/src/register/mstatush.rs index cc64598e..8b50d388 100644 --- a/riscv/src/register/mstatush.rs +++ b/riscv/src/register/mstatush.rs @@ -29,8 +29,8 @@ clear_rv32!(0x310); #[inline] pub unsafe fn set_sbe(endianness: Endianness) { match endianness { - Endianness::BigEndian => _set(1 << 4), - Endianness::LittleEndian => _clear(1 << 4), + Endianness::BigEndian => unsafe { _set(1 << 4) }, + Endianness::LittleEndian => unsafe { _clear(1 << 4) }, } } @@ -38,8 +38,8 @@ pub unsafe fn set_sbe(endianness: Endianness) { #[inline] pub unsafe fn set_mbe(endianness: Endianness) { match endianness { - Endianness::BigEndian => _set(1 << 5), - Endianness::LittleEndian => _clear(1 << 5), + Endianness::BigEndian => unsafe { _set(1 << 5) }, + Endianness::LittleEndian => unsafe { _clear(1 << 5) }, } } diff --git a/riscv/src/register/satp.rs b/riscv/src/register/satp.rs index 48c9cd9f..737074bd 100644 --- a/riscv/src/register/satp.rs +++ b/riscv/src/register/satp.rs @@ -91,7 +91,7 @@ read_write_csr_field! { #[inline] #[cfg(target_pointer_width = "32")] pub unsafe fn set(mode: Mode, asid: usize, ppn: usize) { - try_set(mode, asid, ppn).unwrap(); + unsafe { try_set(mode, asid, ppn) }.unwrap(); } /// Attempts to set the register to corresponding page table mode, physical page number and address space id. @@ -112,7 +112,7 @@ pub unsafe fn try_set(mode: Mode, asid: usize, ppn: usize) -> Result<()> { }) } else { let bits = (mode as usize) << 31 | (asid << 22) | ppn; - _try_write(bits) + unsafe { _try_write(bits) } } } @@ -125,7 +125,7 @@ pub unsafe fn try_set(mode: Mode, asid: usize, ppn: usize) -> Result<()> { #[inline] #[cfg(target_pointer_width = "64")] pub unsafe fn set(mode: Mode, asid: usize, ppn: usize) { - try_set(mode, asid, ppn).unwrap() + unsafe { try_set(mode, asid, ppn) }.unwrap(); } /// Attempts to set the register to corresponding page table mode, physical page number and address space id. @@ -146,7 +146,7 @@ pub unsafe fn try_set(mode: Mode, asid: usize, ppn: usize) -> Result<()> { }) } else { let bits = ((mode as usize) << 60) | (asid << 44) | ppn; - _try_write(bits) + unsafe { _try_write(bits) } } } diff --git a/riscv/src/register/scause.rs b/riscv/src/register/scause.rs index 2d42646f..cf1dcdf1 100644 --- a/riscv/src/register/scause.rs +++ b/riscv/src/register/scause.rs @@ -81,7 +81,7 @@ pub unsafe fn set(cause: Trap) } Trap::Exception(e) => e.number(), }; - _write(bits); + unsafe { _write(bits) }; } #[cfg(test)] diff --git a/riscv/src/register/scounteren.rs b/riscv/src/register/scounteren.rs index e500307a..62011ac9 100644 --- a/riscv/src/register/scounteren.rs +++ b/riscv/src/register/scounteren.rs @@ -54,14 +54,14 @@ set_clear_csr!( /// Panics if `index` is out-of-bounds. #[inline] pub unsafe fn set_hpm(index: usize) { - try_set_hpm(index).unwrap(); + unsafe { try_set_hpm(index) }.unwrap(); } /// Attempts to set the "hpm\[x\]" enable (bits 3-31). #[inline] pub unsafe fn try_set_hpm(index: usize) -> Result<()> { if (3..32).contains(&index) { - _try_set(1 << index) + unsafe { _try_set(1 << index) } } else { Err(Error::IndexOutOfBounds { index, @@ -78,14 +78,14 @@ pub unsafe fn try_set_hpm(index: usize) -> Result<()> { /// Panics if `index` is out-of-bounds. #[inline] pub unsafe fn clear_hpm(index: usize) { - try_clear_hpm(index).unwrap() + unsafe { try_clear_hpm(index) }.unwrap() } /// Attempts to clear the "hpm\[x\]" enable (bits 3-31). #[inline] pub unsafe fn try_clear_hpm(index: usize) -> Result<()> { if (3..32).contains(&index) { - _try_clear(1 << index) + unsafe { _try_clear(1 << index) } } else { Err(Error::IndexOutOfBounds { index, diff --git a/riscv/src/register/sstatus.rs b/riscv/src/register/sstatus.rs index 883004d7..2c75519a 100644 --- a/riscv/src/register/sstatus.rs +++ b/riscv/src/register/sstatus.rs @@ -132,18 +132,18 @@ set_clear_csr!( #[inline] pub unsafe fn set_spp(spp: SPP) { match spp { - SPP::Supervisor => _set(1 << 8), - SPP::User => _clear(1 << 8), + SPP::Supervisor => unsafe { _set(1 << 8) }, + SPP::User => unsafe { _clear(1 << 8) }, } } /// The status of the floating-point unit #[inline] pub unsafe fn set_fs(fs: FS) { - let mut value = _read(); + let mut value = unsafe { _read() }; value &= !(0x3 << 13); // clear previous value value |= (fs as usize) << 13; - _write(value); + unsafe { _write(value) }; } #[cfg(test)] diff --git a/riscv/src/register/stval.rs b/riscv/src/register/stval.rs index c330d183..5fef2cdd 100644 --- a/riscv/src/register/stval.rs +++ b/riscv/src/register/stval.rs @@ -6,5 +6,5 @@ write_csr!(0x143); /// Writes the CSR #[inline] pub unsafe fn write(bits: usize) { - _write(bits) + unsafe { _write(bits) } } diff --git a/riscv/src/register/time.rs b/riscv/src/register/time.rs index ad5e8bbf..0e230a8d 100644 --- a/riscv/src/register/time.rs +++ b/riscv/src/register/time.rs @@ -1,4 +1,4 @@ //! time register read_csr_as_usize!(0xC01); -read_composite_csr!(super::timeh::read(), read()); +read_composite_csr!(super::timeh::read, read); From 8e05b12330686db272b8786fcd6363ce4511a2df Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas=20Rodr=C3=ADguez?= Date: Mon, 16 Jun 2025 17:14:07 +0200 Subject: [PATCH 07/10] Fix Clippy workflow --- .github/workflows/clippy.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.github/workflows/clippy.yaml b/.github/workflows/clippy.yaml index abeb7413..7d55bcb4 100644 --- a/.github/workflows/clippy.yaml +++ b/.github/workflows/clippy.yaml @@ -37,6 +37,10 @@ jobs: strategy: matrix: toolchain: [ stable, nightly ] + include: + # Nightly is only for reference and allowed to fail + - toolchain: nightly + experimental: true runs-on: ubuntu-latest continue-on-error: ${{ matrix.experimental || false }} steps: From 266c394823c6cba0ca7e5e88008ed0865ea858dc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas=20Rodr=C3=ADguez?= Date: Mon, 16 Jun 2025 17:26:49 +0200 Subject: [PATCH 08/10] Adapt riscv-rt to edition 2024 --- .github/workflows/riscv-rt.yaml | 9 ++------- .github/workflows/tests.yaml | 9 ++------- riscv-rt/CHANGELOG.md | 1 + riscv-rt/Cargo.toml | 4 ++-- riscv-rt/README.md | 2 +- riscv-rt/examples/multi_core.rs | 2 +- riscv-rt/macros/Cargo.toml | 2 +- riscv-rt/macros/src/lib.rs | 12 ++++++------ riscv-rt/src/exceptions.rs | 14 +++++++------- riscv-rt/src/lib.rs | 16 ++++++++-------- 10 files changed, 31 insertions(+), 40 deletions(-) diff --git a/.github/workflows/riscv-rt.yaml b/.github/workflows/riscv-rt.yaml index 094d25a1..95d1ae52 100644 --- a/.github/workflows/riscv-rt.yaml +++ b/.github/workflows/riscv-rt.yaml @@ -10,8 +10,8 @@ jobs: build-riscv: strategy: matrix: - # All generated code should be running on stable now, MRSV is 1.67.0 - toolchain: [ stable, nightly, 1.67.0 ] + # All generated code should be running on stable now, MRSV is 1.85.0 + toolchain: [ stable, nightly, 1.85.0 ] target: - riscv32i-unknown-none-elf - riscv32im-unknown-none-elf @@ -27,11 +27,6 @@ jobs: # Nightly is only for reference and allowed to fail - toolchain: nightly experimental: true - exclude: - - toolchain: 1.67.0 - target: riscv32im-unknown-none-elf - - toolchain: 1.67.0 - target: riscv32imafc-unknown-none-elf runs-on: ubuntu-latest continue-on-error: ${{ matrix.experimental || false }} steps: diff --git a/.github/workflows/tests.yaml b/.github/workflows/tests.yaml index 2393f742..0fa44e9d 100644 --- a/.github/workflows/tests.yaml +++ b/.github/workflows/tests.yaml @@ -20,8 +20,8 @@ jobs: run-build: strategy: matrix: - # All generated code should be running on stable now, MRSV is 1.67.0 - toolchain: [ stable, nightly, 1.67.0 ] + # All generated code should be running on stable now, MRSV is 1.85.0 + toolchain: [ stable, nightly, 1.85.0 ] target: - riscv32i-unknown-none-elf - riscv32im-unknown-none-elf @@ -36,11 +36,6 @@ jobs: # Nightly is only for reference and allowed to fail - toolchain: nightly experimental: true - exclude: - - toolchain: 1.67.0 - target: riscv32im-unknown-none-elf - - toolchain: 1.67.0 - target: riscv32imafc-unknown-none-elf runs-on: ubuntu-latest continue-on-error: ${{ matrix.experimental || false }} steps: diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md index 863f2823..72335b3e 100644 --- a/riscv-rt/CHANGELOG.md +++ b/riscv-rt/CHANGELOG.md @@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ### Changed +- Update to Rust edition 2024 (MSRV 1.85) - Main function no longer needs to be close to _start. A linker script may copy all code to RAM and keep .init in flash/ROM. diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml index 761cd52b..c487d93e 100644 --- a/riscv-rt/Cargo.toml +++ b/riscv-rt/Cargo.toml @@ -1,7 +1,7 @@ [package] name = "riscv-rt" version = "0.15.0" -rust-version = "1.67" +rust-version = "1.85" repository = "https://github.com/rust-embedded/riscv" authors = ["The RISC-V Team "] categories = ["embedded", "no-std"] @@ -9,7 +9,7 @@ description = "Minimal runtime / startup for RISC-V CPU's" documentation = "https://docs.rs/riscv-rt" keywords = ["riscv", "runtime", "startup"] license = "ISC" -edition = "2021" +edition = "2024" links = "riscv-rt" # Prevent multiple versions of riscv-rt being linked [package.metadata.docs.rs] diff --git a/riscv-rt/README.md b/riscv-rt/README.md index dedabe95..e81c5746 100644 --- a/riscv-rt/README.md +++ b/riscv-rt/README.md @@ -11,7 +11,7 @@ This project is developed and maintained by the [RISC-V team][team]. ## Minimum Supported Rust Version (MSRV) -This crate is guaranteed to compile on stable Rust 1.61 and up. It *might* +This crate is guaranteed to compile on stable Rust 1.85 and up. It **won't** compile with older versions but that may change in any new patch release. ## License diff --git a/riscv-rt/examples/multi_core.rs b/riscv-rt/examples/multi_core.rs index 0ccfc97a..29a8cd16 100644 --- a/riscv-rt/examples/multi_core.rs +++ b/riscv-rt/examples/multi_core.rs @@ -7,7 +7,7 @@ use riscv::asm::wfi; use riscv::register::{mie, mip}; use riscv_rt::entry; -#[export_name = "_mp_hook"] +#[unsafe(export_name = "_mp_hook")] #[rustfmt::skip] pub extern "Rust" fn user_mp_hook(hartid: usize) -> bool { if hartid == 0 { diff --git a/riscv-rt/macros/Cargo.toml b/riscv-rt/macros/Cargo.toml index 29be4502..40a4f30b 100644 --- a/riscv-rt/macros/Cargo.toml +++ b/riscv-rt/macros/Cargo.toml @@ -11,7 +11,7 @@ license = "MIT OR Apache-2.0" name = "riscv-rt-macros" repository = "https://github.com/rust-embedded/riscv" version = "0.5.0" -edition = "2021" +edition = "2024" [lib] proc-macro = true diff --git a/riscv-rt/macros/src/lib.rs b/riscv-rt/macros/src/lib.rs index dc38e997..66b81798 100644 --- a/riscv-rt/macros/src/lib.rs +++ b/riscv-rt/macros/src/lib.rs @@ -4,11 +4,11 @@ use proc_macro::TokenStream; use proc_macro2::{Span, TokenStream as TokenStream2}; use quote::quote; use syn::{ + FnArg, ItemFn, LitInt, LitStr, PatType, Path, ReturnType, Token, Type, Visibility, parse::{self, Parse}, parse_macro_input, parse_quote, punctuated::Punctuated, spanned::Spanned, - FnArg, ItemFn, LitInt, LitStr, PatType, Path, ReturnType, Token, Type, Visibility, }; /// Attribute to declare the entry point of the program @@ -142,7 +142,7 @@ pub fn entry(args: TokenStream, input: TokenStream) -> TokenStream { quote!( #[allow(non_snake_case)] - #[export_name = "main"] + #[unsafe(export_name = "main")] #(#attrs)* pub #unsafety fn __risc_v_rt__main(#args) -> ! { #(#stmts)* @@ -254,7 +254,7 @@ pub fn pre_init(args: TokenStream, input: TokenStream) -> TokenStream { let block = f.block; quote!( - #[export_name = "__pre_init"] + #[unsafe(export_name = "__pre_init")] #(#attrs)* pub unsafe fn #ident() #block ) @@ -457,7 +457,7 @@ fn store_trap bool>(arch: RiscvArch, mut filter: T) -> String arch.trap_frame() .iter() .enumerate() - .filter(|(_, ®)| !reg.starts_with('_') && filter(reg)) + .filter(|(_, reg)| !reg.starts_with('_') && filter(reg)) .map(|(i, reg)| format!("{store} {reg}, {i}*{width}(sp)")) .collect::>() .join("\n ") @@ -471,7 +471,7 @@ fn load_trap(arch: RiscvArch) -> String { arch.trap_frame() .iter() .enumerate() - .filter(|(_, ®)| !reg.starts_with('_')) + .filter(|(_, reg)| !reg.starts_with('_')) .map(|(i, reg)| format!("{load} {reg}, {i}*{width}(sp)")) .collect::>() .join("\n ") @@ -766,7 +766,7 @@ fn trap( #start_trap - #[export_name = #export_name] + #[unsafe(export_name = #export_name)] #f ) .into() diff --git a/riscv-rt/src/exceptions.rs b/riscv-rt/src/exceptions.rs index e499db81..7c6a836b 100644 --- a/riscv-rt/src/exceptions.rs +++ b/riscv-rt/src/exceptions.rs @@ -13,7 +13,7 @@ use crate::TrapFrame; -extern "C" { +unsafe extern "C" { fn InstructionMisaligned(trap_frame: &TrapFrame); fn InstructionFault(trap_frame: &TrapFrame); fn IllegalInstruction(trap_frame: &TrapFrame); @@ -31,7 +31,7 @@ extern "C" { } /// Array with all the exception handlers sorted according to their exception source code. -#[no_mangle] +#[unsafe(no_mangle)] pub static __EXCEPTIONS: [Option; 16] = [ Some(InstructionMisaligned), Some(InstructionFault), @@ -57,13 +57,13 @@ pub static __EXCEPTIONS: [Option; 16] = [ /// /// This function must be called only from the [`crate::start_trap_rust`] function. /// Do **NOT** call this function directly. -#[no_mangle] +#[unsafe(no_mangle)] pub unsafe extern "C" fn _dispatch_exception(trap_frame: &TrapFrame, code: usize) { - extern "C" { - fn ExceptionHandler(trap_frame: &TrapFrame); + unsafe extern "C" { + unsafe fn ExceptionHandler(trap_frame: &TrapFrame); } match __EXCEPTIONS.get(code) { - Some(Some(handler)) => handler(trap_frame), - _ => ExceptionHandler(trap_frame), + Some(Some(handler)) => unsafe { handler(trap_frame) }, + _ => unsafe { ExceptionHandler(trap_frame) }, } } diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs index 406adda6..b32218d5 100644 --- a/riscv-rt/src/lib.rs +++ b/riscv-rt/src/lib.rs @@ -592,7 +592,7 @@ pub use riscv_rt_macros::pre_init; /// two copies of riscv-rt together, linking will fail. We also declare a links key in /// Cargo.toml which is the more modern way to solve the same problem, but we have to keep /// __ONCE__ around to prevent linking with versions before the links key was added. -#[export_name = "error: riscv-rt appears more than once in the dependency graph"] +#[unsafe(export_name = "error: riscv-rt appears more than once in the dependency graph")] #[doc(hidden)] pub static __ONCE__: () = (); @@ -672,11 +672,11 @@ pub struct TrapFrame { /// Do **NOT** call this function directly. #[cfg_attr( any(target_arch = "riscv32", target_arch = "riscv64"), - link_section = ".trap.rust" + unsafe(link_section = ".trap.rust") )] -#[export_name = "_start_trap_rust"] +#[unsafe(export_name = "_start_trap_rust")] pub unsafe extern "C" fn start_trap_rust(trap_frame: *const TrapFrame) { - extern "C" { + unsafe extern "C" { #[cfg(not(feature = "v-trap"))] fn _dispatch_core_interrupt(code: usize); #[cfg(feature = "v-trap")] @@ -686,10 +686,10 @@ pub unsafe extern "C" fn start_trap_rust(trap_frame: *const TrapFrame) { match xcause::read().cause() { #[cfg(not(feature = "v-trap"))] - xcause::Trap::Interrupt(code) => _dispatch_core_interrupt(code), + xcause::Trap::Interrupt(code) => unsafe { _dispatch_core_interrupt(code) }, #[cfg(feature = "v-trap")] - xcause::Trap::Interrupt(_) => DefaultHandler(), - xcause::Trap::Exception(code) => _dispatch_exception(&*trap_frame, code), + xcause::Trap::Interrupt(_) => unsafe { DefaultHandler() }, + xcause::Trap::Exception(code) => unsafe { _dispatch_exception(&*trap_frame, code) }, } } @@ -698,7 +698,7 @@ pub unsafe extern "C" fn start_trap_rust(trap_frame: *const TrapFrame) { /// The returned pointer is guaranteed to be 4-byte aligned. #[inline] pub fn heap_start() -> *mut usize { - extern "C" { + unsafe extern "C" { static mut __sheap: usize; } From 23ac3cb4e8274eefc5523dbe94c719ccc512c9d4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas=20Rodr=C3=ADguez?= Date: Mon, 16 Jun 2025 17:46:42 +0200 Subject: [PATCH 09/10] Update test crates --- tests-build/Cargo.toml | 2 +- tests-build/src/lib.rs | 2 +- tests-trybuild/Cargo.toml | 2 +- tests-trybuild/tests/riscv/pass_test.rs | 10 +++++----- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/tests-build/Cargo.toml b/tests-build/Cargo.toml index 4798fa37..d8ba5e4c 100644 --- a/tests-build/Cargo.toml +++ b/tests-build/Cargo.toml @@ -1,7 +1,7 @@ [package] name = "tests-build" version = "0.1.0" -edition = "2021" +edition = "2024" [dependencies] panic-halt = "1.0" diff --git a/tests-build/src/lib.rs b/tests-build/src/lib.rs index ae51a665..1a5477cb 100644 --- a/tests-build/src/lib.rs +++ b/tests-build/src/lib.rs @@ -43,5 +43,5 @@ pub enum Exception { } #[cfg(feature = "pre-init")] -#[cfg_attr(feature = "pre-init", riscv_rt::pre_init)] +#[riscv_rt::pre_init] unsafe fn pre_init() {} diff --git a/tests-trybuild/Cargo.toml b/tests-trybuild/Cargo.toml index c5141b43..e7d845c2 100644 --- a/tests-trybuild/Cargo.toml +++ b/tests-trybuild/Cargo.toml @@ -1,7 +1,7 @@ [package] name = "tests-trybuild" version = "0.1.0" -edition = "2021" +edition = "2024" [dependencies] riscv = { path = "../riscv" } diff --git a/tests-trybuild/tests/riscv/pass_test.rs b/tests-trybuild/tests/riscv/pass_test.rs index c80ead3e..337331da 100644 --- a/tests-trybuild/tests/riscv/pass_test.rs +++ b/tests-trybuild/tests/riscv/pass_test.rs @@ -35,19 +35,19 @@ enum HartId { } mod isr { - #[export_name = "DefaultHandler"] + #[unsafe(export_name = "DefaultHandler")] fn default_handler() {} - #[export_name = "I1"] + #[unsafe(export_name = "I1")] fn i1() {} - #[export_name = "I2"] + #[unsafe(export_name = "I2")] fn i2() {} - #[export_name = "I4"] + #[unsafe(export_name = "I4")] fn i4() {} - #[export_name = "I7"] + #[unsafe(export_name = "I7")] fn i7() {} } From 4cbdce4010b965f39305be5bb16fbe2d50ee1689 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas=20Rodr=C3=ADguez?= Date: Tue, 17 Jun 2025 15:30:02 +0200 Subject: [PATCH 10/10] Avoid clippy warnings in Nightly --- riscv-rt/macros/src/lib.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/riscv-rt/macros/src/lib.rs b/riscv-rt/macros/src/lib.rs index 66b81798..f28f020d 100644 --- a/riscv-rt/macros/src/lib.rs +++ b/riscv-rt/macros/src/lib.rs @@ -1,4 +1,5 @@ #![deny(warnings)] +#![allow(clippy::collapsible_if)] // to avoid warnings in Nightly builds use proc_macro::TokenStream; use proc_macro2::{Span, TokenStream as TokenStream2};