Update to Rust edition 2024

.github/workflows/clippy.yaml

@@ -37,6 +37,10 @@ jobs:
     strategy:
       matrix:
         toolchain: [ stable, nightly ]
+        include:
+          # Nightly is only for reference and allowed to fail
+          - toolchain: nightly
+            experimental: true
     runs-on: ubuntu-latest
     continue-on-error: ${{ matrix.experimental || false }}
     steps:

.github/workflows/riscv-peripheral.yaml

@@ -11,8 +11,8 @@ jobs:
   build-riscv:
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.75.0
-        toolchain: [ stable, nightly, 1.75.0 ]
+        # All generated code should be running on stable now, MRSV is 1.85.0
+        toolchain: [ stable, nightly, 1.85.0 ]
         target:
           - riscv32i-unknown-none-elf
           - riscv32imc-unknown-none-elf

.github/workflows/riscv-rt.yaml

@@ -10,8 +10,8 @@ jobs:
   build-riscv:
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.67.0
-        toolchain: [ stable, nightly, 1.67.0 ]
+        # All generated code should be running on stable now, MRSV is 1.85.0
+        toolchain: [ stable, nightly, 1.85.0 ]
         target:
           - riscv32i-unknown-none-elf
           - riscv32im-unknown-none-elf
@@ -27,11 +27,6 @@ jobs:
           # Nightly is only for reference and allowed to fail
           - toolchain: nightly
             experimental: true
-        exclude:
-          - toolchain: 1.67.0
-            target: riscv32im-unknown-none-elf
-          - toolchain: 1.67.0
-            target: riscv32imafc-unknown-none-elf
     runs-on: ubuntu-latest
     continue-on-error: ${{ matrix.experimental || false }}
     steps:

.github/workflows/riscv-semihosting.yaml

@@ -11,8 +11,8 @@ jobs:
   build-riscv:
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.67.0
-        toolchain: [ stable, nightly, 1.67.0 ]
+        # All generated code should be running on stable now, MRSV is 1.85.0
+        toolchain: [ stable, nightly, 1.85.0 ]
         target:
           - riscv32i-unknown-none-elf
           - riscv32imc-unknown-none-elf

.github/workflows/riscv-target-parser.yaml

@@ -11,7 +11,7 @@ jobs:
     strategy:
       matrix:
         os: [ macos-latest, ubuntu-latest, windows-latest ]
-        toolchain: [ stable, nightly, 1.67.0 ]
+        toolchain: [ stable, nightly, 1.85.0 ]
         include:
           # Nightly is only for reference and allowed to fail
           - rust: nightly

.github/workflows/riscv.yaml

@@ -11,8 +11,8 @@ jobs:
   build-riscv:
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.67.0
-        toolchain: [ stable, nightly, 1.67.0 ]
+        # All generated code should be running on stable now, MRSV is 1.85.0
+        toolchain: [ stable, nightly, 1.85.0 ]
         target:
           - riscv32i-unknown-none-elf
           - riscv32imc-unknown-none-elf

.github/workflows/tests.yaml

@@ -20,8 +20,8 @@ jobs:
   run-build:
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.67.0
-        toolchain: [ stable, nightly, 1.67.0 ]
+        # All generated code should be running on stable now, MRSV is 1.85.0
+        toolchain: [ stable, nightly, 1.85.0 ]
         target:
           - riscv32i-unknown-none-elf
           - riscv32im-unknown-none-elf
@@ -36,11 +36,6 @@ jobs:
           # Nightly is only for reference and allowed to fail
           - toolchain: nightly
             experimental: true
-        exclude:
-          - toolchain: 1.67.0
-            target: riscv32im-unknown-none-elf
-          - toolchain: 1.67.0
-            target: riscv32imafc-unknown-none-elf
     runs-on: ubuntu-latest
     continue-on-error: ${{ matrix.experimental || false }}
     steps:

riscv-pac/CHANGELOG.md

@@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Changed
+
+- Update to Rust edition 2024 (MSRV 1.85)
+
 ## [v0.2.0] - 2024-10-19
 
 ### Added

riscv-pac/Cargo.toml

@@ -1,8 +1,8 @@
 [package]
 name = "riscv-pac"
 version = "0.2.0"
-edition = "2021"
-rust-version = "1.60"
+edition = "2024"
+rust-version = "1.85"
 repository = "https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "hardware-support", "no-std"]

riscv-pac/README.md

@@ -11,7 +11,7 @@ This project is developed and maintained by the [RISC-V team][team].
 
 ## Minimum Supported Rust Version (MSRV)
 
-This crate is guaranteed to compile on stable Rust 1.60 and up. It *might*
+This crate is guaranteed to compile on stable Rust 1.85 and up. It **won't**
 compile with older versions but that may change in any new patch release.
 
 ## License

riscv-peripheral/CHANGELOG.md

@@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Changed
+
+- Update to Rust edition 2024 (MSRV 1.85)
+
 ## [v0.3.0] - 2025-06-10
 
 ### Changed

riscv-peripheral/Cargo.toml

@@ -1,8 +1,8 @@
 [package]
 name = "riscv-peripheral"
 version = "0.3.0"
-edition = "2021"
-rust-version = "1.75"
+edition = "2024"
+rust-version = "1.85"
 repository = "https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "hardware-support", "no-std"]

riscv-peripheral/README.md

@@ -11,7 +11,7 @@ This project is developed and maintained by the [RISC-V team][team].
 
 ## Minimum Supported Rust Version (MSRV)
 
-This crate is guaranteed to compile on stable Rust 1.75 and up. It *might*
+This crate is guaranteed to compile on stable Rust 1.85 and up. It **won't**
 compile with older versions but that may change in any new patch release.
 
 ## License

riscv-peripheral/src/aclint.rs

@@ -78,8 +78,10 @@ impl<C: Clint> CLINT<C> {
     /// Enabling the `CLINT` may break mask-based critical sections.
     #[inline]
     pub unsafe fn enable(self) {
-        self.mswi().enable();
-        self.mtimer().enable();
+        unsafe {
+            self.mswi().enable();
+            self.mtimer().enable();
+        }
     }
 
     /// Disables machine timer **AND** software interrupts to prevent the CLINT from triggering interrupts.

riscv-peripheral/src/aclint/mswi.rs

@@ -64,7 +64,7 @@ impl<M: Mswi> MSWI<M> {
     /// Enabling interrupts may break mask-based critical sections.
     #[inline]
     pub unsafe fn enable(self) {
-        mie::set_msoft();
+        unsafe { mie::set_msoft() };
     }
 
     /// Disables machine software interrupts in the current HART.

riscv-peripheral/src/aclint/mtimer.rs

@@ -81,7 +81,7 @@ impl<M: Mtimer> MTIMER<M> {
     /// Enabling interrupts may break mask-based critical sections.
     #[inline]
     pub unsafe fn enable(self) {
-        mie::set_mtimer();
+        unsafe { mie::set_mtimer() };
     }
 
     /// Disables machine timer interrupts in the current HART.

riscv-peripheral/src/aclint/sswi.rs

@@ -55,7 +55,7 @@ impl<S: Sswi> SSWI<S> {
     /// Enabling interrupts may break mask-based critical sections.
     #[inline]
     pub unsafe fn enable(self) {
-        sie::set_ssoft();
+        unsafe { sie::set_ssoft() };
     }
 
     /// Disables supervisor software interrupts in the current HART.

riscv-peripheral/src/common.rs

@@ -265,7 +265,7 @@ macro_rules! peripheral {
             #[inline]
             pub const unsafe fn new(address: usize) -> Self {
                 Self {
-                    register: $crate::common::Reg::new(address as _),
+                    register: unsafe { $crate::common::Reg::new(address as _) },
                 }
             }
         }

riscv-peripheral/src/hal/aclint.rs

@@ -1,6 +1,6 @@
 //! Delay trait implementation for (A)CLINT peripherals
 
-use crate::aclint::mtimer::{Mtimer, MTIMER};
+use crate::aclint::mtimer::{MTIMER, Mtimer};
 use crate::hal::delay::DelayNs;
 
 impl<M: Mtimer> DelayNs for MTIMER<M> {

riscv-peripheral/src/plic.rs

@@ -72,7 +72,7 @@ impl<P: Plic> PLIC<P> {
     /// Enabling the `PLIC` may break mask-based critical sections.
     #[inline]
     pub unsafe fn enable(self) {
-        mie::set_mext();
+        unsafe { mie::set_mext() };
     }
 
     /// Disables machine external interrupts to prevent the PLIC from triggering interrupts.

riscv-peripheral/src/plic/enables.rs

@@ -1,6 +1,6 @@
 //! Interrupt enables register of a PLIC context.
 
-use crate::common::{Reg, RW};
+use crate::common::{RW, Reg};
 use riscv_pac::ExternalInterruptNumber;
 
 /// Enables register of a PLIC context.
@@ -77,7 +77,7 @@ impl ENABLES {
         let offset = (source / u32::BITS as usize) as _;
         // SAFETY: valid interrupt number
         let reg: Reg<u32, RW> = unsafe { Reg::new(self.ptr.offset(offset)) };
-        reg.atomic_set_bit(source % u32::BITS as usize, order);
+        unsafe { reg.atomic_set_bit(source % u32::BITS as usize, order) };
     }
 
     /// Disables an interrupt source for the PLIC context.
@@ -115,7 +115,7 @@ impl ENABLES {
         let offset = (source / u32::BITS as usize) as _;
         // SAFETY: valid interrupt number
         let reg: Reg<u32, RW> = unsafe { Reg::new(self.ptr.offset(offset)) };
-        reg.atomic_clear_bit(source % u32::BITS as usize, order);
+        unsafe { reg.atomic_clear_bit(source % u32::BITS as usize, order) };
     }
 
     /// Enables all the external interrupt sources for the PLIC context.

riscv-peripheral/src/plic/pendings.rs

@@ -1,6 +1,6 @@
 //! Interrupt pending bits register.
 
-use crate::common::{Reg, RO};
+use crate::common::{RO, Reg};
 use riscv_pac::ExternalInterruptNumber;
 
 /// Interrupts pending bits register.

riscv-peripheral/src/plic/priorities.rs

@@ -1,6 +1,6 @@
 //! Interrupts Priorities register.
 
-use crate::common::{Reg, RW};
+use crate::common::{RW, Reg};
 use riscv_pac::{ExternalInterruptNumber, PriorityNumber};
 
 /// Interrupts priorities register.

riscv-rt/CHANGELOG.md

@@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Changed
 
+- Update to Rust edition 2024 (MSRV 1.85)
 - Main function no longer needs to be close to _start. A linker script may copy
   all code to RAM and keep .init in flash/ROM.
 

riscv-rt/Cargo.toml

@@ -1,15 +1,15 @@
 [package]
 name = "riscv-rt"
 version = "0.15.0"
-rust-version = "1.67"
+rust-version = "1.85"
 repository = "https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "no-std"]
 description = "Minimal runtime / startup for RISC-V CPU's"
 documentation = "https://docs.rs/riscv-rt"
 keywords = ["riscv", "runtime", "startup"]
 license = "ISC"
-edition = "2021"
+edition = "2024"
 links = "riscv-rt" # Prevent multiple versions of riscv-rt being linked
 
 [package.metadata.docs.rs]

riscv-rt/README.md

@@ -11,7 +11,7 @@ This project is developed and maintained by the [RISC-V team][team].
 
 ## Minimum Supported Rust Version (MSRV)
 
-This crate is guaranteed to compile on stable Rust 1.61 and up. It *might*
+This crate is guaranteed to compile on stable Rust 1.85 and up. It **won't**
 compile with older versions but that may change in any new patch release.
 
 ## License

riscv-rt/examples/multi_core.rs

@@ -7,7 +7,7 @@ use riscv::asm::wfi;
 use riscv::register::{mie, mip};
 use riscv_rt::entry;
 
-#[export_name = "_mp_hook"]
+#[unsafe(export_name = "_mp_hook")]
 #[rustfmt::skip]
 pub extern "Rust" fn user_mp_hook(hartid: usize) -> bool {
     if hartid == 0 {

riscv-rt/macros/Cargo.toml

@@ -11,7 +11,7 @@ license = "MIT OR Apache-2.0"
 name = "riscv-rt-macros"
 repository = "https://github.com/rust-embedded/riscv"
 version = "0.5.0"
-edition = "2021"
+edition = "2024"
 
 [lib]
 proc-macro = true

riscv-rt/macros/src/lib.rs

@@ -1,14 +1,15 @@
 #![deny(warnings)]
+#![allow(clippy::collapsible_if)] // to avoid warnings in Nightly builds
 
 use proc_macro::TokenStream;
 use proc_macro2::{Span, TokenStream as TokenStream2};
 use quote::quote;
 use syn::{
+    FnArg, ItemFn, LitInt, LitStr, PatType, Path, ReturnType, Token, Type, Visibility,
     parse::{self, Parse},
     parse_macro_input, parse_quote,
     punctuated::Punctuated,
     spanned::Spanned,
-    FnArg, ItemFn, LitInt, LitStr, PatType, Path, ReturnType, Token, Type, Visibility,
 };
 
 /// Attribute to declare the entry point of the program
@@ -142,7 +143,7 @@ pub fn entry(args: TokenStream, input: TokenStream) -> TokenStream {
 
     quote!(
         #[allow(non_snake_case)]
-        #[export_name = "main"]
+        #[unsafe(export_name = "main")]
         #(#attrs)*
         pub #unsafety fn __risc_v_rt__main(#args) -> ! {
             #(#stmts)*
@@ -254,7 +255,7 @@ pub fn pre_init(args: TokenStream, input: TokenStream) -> TokenStream {
     let block = f.block;
 
     quote!(
-        #[export_name = "__pre_init"]
+        #[unsafe(export_name = "__pre_init")]
         #(#attrs)*
         pub unsafe fn #ident() #block
     )
@@ -457,7 +458,7 @@ fn store_trap<T: FnMut(&str) -> bool>(arch: RiscvArch, mut filter: T) -> String
     arch.trap_frame()
         .iter()
         .enumerate()
-        .filter(|(_, &reg)| !reg.starts_with('_') && filter(reg))
+        .filter(|(_, reg)| !reg.starts_with('_') && filter(reg))
         .map(|(i, reg)| format!("{store} {reg}, {i}*{width}(sp)"))
         .collect::<Vec<_>>()
         .join("\n    ")
@@ -471,7 +472,7 @@ fn load_trap(arch: RiscvArch) -> String {
     arch.trap_frame()
         .iter()
         .enumerate()
-        .filter(|(_, &reg)| !reg.starts_with('_'))
+        .filter(|(_, reg)| !reg.starts_with('_'))
         .map(|(i, reg)| format!("{load} {reg}, {i}*{width}(sp)"))
         .collect::<Vec<_>>()
         .join("\n    ")
@@ -766,7 +767,7 @@ fn trap(
 
         #start_trap
 
-        #[export_name = #export_name]
+        #[unsafe(export_name = #export_name)]
         #f
     )
     .into()